From dc04949d782f03a56fa139b438bab315489ea4d2 Mon Sep 17 00:00:00 2001
From: Gwenhael Goavec-Merou <gwenhael@enjoy-digital.fr>
Date: Thu, 25 Jul 2024 14:11:06 +0200
Subject: [PATCH] build/altera/common,platform: added ddrinput/ddrout
 primitives

---
 litex/build/altera/common.py   | 71 +++++++++++++++++++++++++++++++++-
 litex/build/altera/platform.py |  2 +
 2 files changed, 72 insertions(+), 1 deletion(-)

diff --git a/litex/build/altera/common.py b/litex/build/altera/common.py
index 3ed0947ba..f0f246edb 100644
--- a/litex/build/altera/common.py
+++ b/litex/build/altera/common.py
@@ -99,7 +99,6 @@ class AlteraDDROutputImpl(Module):
             o_dataout  = o,
         )
 
-
 class AlteraDDROutput:
     @staticmethod
     def lower(dr):
@@ -147,3 +146,73 @@ altera_special_overrides = {
     SDROutput:              AlteraSDROutput,
     SDRInput:               AlteraSDRInput,
 }
+
+# Agilex5 DDROutput --------------------------------------------------------------------------------
+
+class Agilex5DDROutputImpl(Module):
+    def __init__(self, i1, i2, o, clk):
+        self.specials += Instance("tennm_ph2_ddio_out",
+            p_mode      = "MODE_DDR",
+            p_asclr_ena = "ASCLR_ENA_NONE",
+            p_sclr_ena  = "SCLR_ENA_NONE",
+            o_dataout   = o,
+            i_datainlo  = i2,
+            i_datainhi  = i1,
+            i_clk       = clk,
+            i_ena       = Constant(1, 1),
+            i_areset    = Constant(1, 1),
+            i_sreset    = Constant(1, 1),
+        )
+
+class Agilex5DDROutput:
+    @staticmethod
+    def lower(dr):
+        return Agilex5DDROutputImpl(dr.i1, dr.i2, dr.o, dr.clk)
+
+# Agilex5 DDRInput ---------------------------------------------------------------------------------
+
+class Agilex5DDRInputImpl(Module):
+    def __init__(self, i, o1, o2, clk):
+        self.specials += Instance("tennm_ph2_ddio_in",
+            p_mode      = "MODE_DDR",
+            p_asclr_ena = "ASCLR_ENA_NONE",
+            p_sclr_ena  = "SCLR_ENA_NONE",
+            i_clk       = clk,
+            i_datain    = i,
+            o_regouthi  = o1,
+            o_regoutlo  = o2,
+            i_ena       = Constant(1, 1),
+            i_areset    = Constant(1, 1),
+            i_sreset    = Constant(1, 1),
+        )
+
+class Agilex5DDRInput:
+    @staticmethod
+    def lower(dr):
+        return Agilex5DDRInputImpl(dr.i, dr.o1, dr.o2, dr.clk)
+
+# Agilex5 SDROutput --------------------------------------------------------------------------------
+
+class Agilex5SDROutput:
+    @staticmethod
+    def lower(dr):
+        return Agilex5DDROutputImpl(dr.i, dr.i, dr.o, dr.clk)
+
+# Agilex5 SDRInput ---------------------------------------------------------------------------------
+
+class Agilex5SDRInput:
+    @staticmethod
+    def lower(dr):
+        return Agilex5DDRInputImpl(dr.i, dr.o, Signal(), dr.clk)
+
+# Agilex5 Special Overrides ------------------------------------------------------------------------
+
+agilex5_special_overrides = {
+    AsyncResetSynchronizer: AlteraAsyncResetSynchronizer,
+    DifferentialInput:      AlteraDifferentialInput,
+    DifferentialOutput:     AlteraDifferentialOutput,
+    DDROutput:              Agilex5DDROutput,
+    DDRInput:               Agilex5DDRInput,
+    SDROutput:              Agilex5SDROutput,
+    SDRInput:               Agilex5SDRInput,
+}
diff --git a/litex/build/altera/platform.py b/litex/build/altera/platform.py
index e023d2ced..f7b3b0a8e 100644
--- a/litex/build/altera/platform.py
+++ b/litex/build/altera/platform.py
@@ -34,6 +34,8 @@ class AlteraPlatform(GenericPlatform):
 
     def get_verilog(self, *args, special_overrides=dict(), **kwargs):
         so = dict(common.altera_special_overrides)
+        if self.device[:3] == "A5E":
+            so.update(common.agilex5_special_overrides)
         so.update(special_overrides)
         return GenericPlatform.get_verilog(self, *args,
             special_overrides = so,