From e141826fd8157b35b3be4076860e063439516a03 Mon Sep 17 00:00:00 2001 From: Piotr Wojnarowski Date: Wed, 22 Jun 2022 13:19:46 +0200 Subject: [PATCH 1/9] software/liblitesdcard: Fix condition in sdcard_init Instead of retrying `sdcard_app_send_op_cond` until it returns an error, retry until it completes successfully and the command response has the busy bit set. --- litex/soc/software/liblitesdcard/sdcard.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/litex/soc/software/liblitesdcard/sdcard.c b/litex/soc/software/liblitesdcard/sdcard.c index b7b169a90..b030dca39 100644 --- a/litex/soc/software/liblitesdcard/sdcard.c +++ b/litex/soc/software/liblitesdcard/sdcard.c @@ -382,6 +382,7 @@ void sdcard_decode_csd(void) { int sdcard_init(void) { uint16_t rca, timeout; + uint32_t r[SD_CMD_RESPONSE_SIZE/4]; /* Set SD clk freq to Initialization frequency */ sdcard_set_clk_freq(SDCARD_CLK_FREQ_INIT, 0); @@ -411,8 +412,13 @@ int sdcard_init(void) { /* Set SDCard in Operational state */ for (timeout=1000; timeout>0; timeout--) { sdcard_app_cmd(0); - if (sdcard_app_send_op_cond(1) != SD_OK) - break; + if (sdcard_app_send_op_cond(1) == SD_OK) { + csr_rd_buf_uint32(CSR_SDCORE_CMD_RESPONSE_ADDR, + r, SD_CMD_RESPONSE_SIZE/4); + + if (r[3] & 0x80000000) /* Busy bit, set when init is complete */ + break; + } busy_wait(1); } if (timeout == 0) From c4e3962deff5ad2d7f4c1ad8c76117b503632279 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Mon, 27 Jun 2022 15:46:57 +0200 Subject: [PATCH 2/9] soc/add_etherbone: Expose IP Broadcast capability. --- litex/soc/integration/soc.py | 2 ++ 1 file changed, 2 insertions(+) diff --git a/litex/soc/integration/soc.py b/litex/soc/integration/soc.py index cdd2d3cb4..d20e33680 100644 --- a/litex/soc/integration/soc.py +++ b/litex/soc/integration/soc.py @@ -1638,6 +1638,7 @@ class LiteXSoC(SoC): ip_address = "192.168.1.50", udp_port = 1234, buffer_depth = 16, + with_ip_broadcast = True, with_timing_constraints = True): # Imports from liteeth.core import LiteEthUDPIPCore @@ -1654,6 +1655,7 @@ class LiteXSoC(SoC): ip_address = ip_address, clk_freq = self.clk_freq, dw = data_width, + with_ip_broadcast = with_ip_broadcast, with_sys_datapath = with_sys_datapath, ) if not with_sys_datapath: From 4ff839900b9073c2e6935fada49f922ec5584463 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Mon, 27 Jun 2022 17:49:39 +0200 Subject: [PATCH 3/9] bios/cmd_litedram: Enable sdram_init/mr_write commands also for SDRAM. --- litex/soc/software/bios/cmds/cmd_litedram.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/litex/soc/software/bios/cmds/cmd_litedram.c b/litex/soc/software/bios/cmds/cmd_litedram.c index 3d6c468ff..132015b17 100644 --- a/litex/soc/software/bios/cmds/cmd_litedram.c +++ b/litex/soc/software/bios/cmds/cmd_litedram.c @@ -23,7 +23,7 @@ * Initialize SDRAM (Init + Calibration) * */ -#if defined(CSR_SDRAM_BASE) && defined(CSR_DDRPHY_BASE) +#if defined(CSR_SDRAM_BASE) define_command(sdram_init, sdram_init, "Initialize SDRAM (Init + Calibration)", LITEDRAM_CMDS); #endif @@ -317,7 +317,7 @@ define_command(sdram_force_bitslip, sdram_force_bitslip_handler, "Force write le * Write SDRAM Mode Register * */ -#if defined(CSR_SDRAM_BASE) && defined(CSR_DDRPHY_BASE) +#if defined(CSR_SDRAM_BASE) static void sdram_mr_write_handler(int nb_params, char **params) { char *c; From 60d0c4ddd443e2256ea3018185d1d366e2415234 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Mon, 27 Jun 2022 17:50:29 +0200 Subject: [PATCH 4/9] ci: Compile/Install Verilator from sources (Required for updated Vexriscv-SMP). --- .github/workflows/ci.yml | 17 ++++++++++++++++- 1 file changed, 16 insertions(+), 1 deletion(-) diff --git a/.github/workflows/ci.yml b/.github/workflows/ci.yml index 24068961e..308939f4b 100644 --- a/.github/workflows/ci.yml +++ b/.github/workflows/ci.yml @@ -10,11 +10,15 @@ jobs: - name: Checkout uses: actions/checkout@v2 + - name: Setup CCache + uses: hendrikmuhs/ccache-action@v1 + # Install Tools - name: Install Tools run: | sudo apt-get install wget build-essential python3 ninja-build - sudo apt-get install verilator libevent-dev libjson-c-dev + sudo apt-get install libevent-dev libjson-c-dev flex bison + sudo apt-get install libfl-dev libfl2 zlibc zlib1g-dev pip3 install setuptools pip3 install requests pip3 install pexpect @@ -35,6 +39,17 @@ jobs: sudo mkdir /usr/local/openrisc sudo cp -r $PWD/../openrisc-*/* /usr/local/openrisc + # Build / Install Verilator + - name: Build Verilator + run: | + export PATH="/usr/lib/ccache:/usr/local/opt/ccache/libexec:$PATH" + git clone https://github.com/verilator/verilator + cd verilator + autoconf + ./configure + make -j$(nproc) + sudo make install + # Install Project - name: Install Project run: python3 setup.py develop --user From f8984233901718fdf04ab49212cf45df0b82aaa5 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Mon, 27 Jun 2022 19:54:50 +0200 Subject: [PATCH 5/9] test/test_cpu: Diable mor1kx/picorv32 for now due to issue with newer Verilator. --- test/test_cpu.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/test/test_cpu.py b/test/test_cpu.py index ae0c168e2..2c3c88b2b 100644 --- a/test/test_cpu.py +++ b/test/test_cpu.py @@ -41,9 +41,7 @@ class TestCPU(unittest.TestCase): "firev", # (riscv / softcore) "ibex", # (riscv / softcore) "marocchino", # (or1k / softcore) - "mor1kx", # (or1k / softcore) "naxriscv", # (riscv / softcore) - "picorv32", # (riscv / softcore) "rocket", # (riscv / softcore) "serv", # (riscv / softcore) "vexriscv", # (riscv / softcore) @@ -61,7 +59,9 @@ class TestCPU(unittest.TestCase): "lm32", # (lm32 / softcore) -> Requires LM32 toolchain. "microwatt", # (ppc64 / softcore) -> Requires PPC toolchain + VHDL->Verilog (GHDL + Yosys). "minerva", # (riscv / softcore) -> Broken install? (Amaranth?) + "mor1kx", # (or1k / softcore) -> Verilator compilation issue. "neorv32", # (riscv / softcore) -> Requires VHDL->Verilog (GHDL + Yosys). + "picorv32", # (riscv / softcore) -> Verilator compilation issue. "zynq7000", # (arm / hardcore) -> Hardcore. "zynqmp", # (aarch64 / hardcore) -> Hardcore. ] From ec9d1c4fd07591d8b6c3da72492d56f853796492 Mon Sep 17 00:00:00 2001 From: enjoy-digital Date: Mon, 27 Jun 2022 22:43:01 +0200 Subject: [PATCH 6/9] CI: Disable more CPUs. --- test/test_cpu.py | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/test/test_cpu.py b/test/test_cpu.py index 2c3c88b2b..b28ae4326 100644 --- a/test/test_cpu.py +++ b/test/test_cpu.py @@ -36,13 +36,13 @@ class TestCPU(unittest.TestCase): def test_cpu(self): tested_cpus = [ - "cv32e40p", # (riscv / softcore) + #"cv32e40p", # (riscv / softcore) "femtorv", # (riscv / softcore) "firev", # (riscv / softcore) "ibex", # (riscv / softcore) - "marocchino", # (or1k / softcore) + #"marocchino", # (or1k / softcore) "naxriscv", # (riscv / softcore) - "rocket", # (riscv / softcore) + #"rocket", # (riscv / softcore) "serv", # (riscv / softcore) "vexriscv", # (riscv / softcore) "vexriscv_smp", # (riscv / softcore) From aec8cd5339fa1bfe280bb0aafafef2f03e4a84c8 Mon Sep 17 00:00:00 2001 From: Christian Klarhorst Date: Tue, 28 Jun 2022 15:26:14 +0200 Subject: [PATCH 7/9] build/xilinx/ise: Fix yosys flow The top name changed in 2016 but only XST was changed. --- litex/build/xilinx/ise.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) mode change 100644 => 100755 litex/build/xilinx/ise.py diff --git a/litex/build/xilinx/ise.py b/litex/build/xilinx/ise.py old mode 100644 new mode 100755 index 5c6b01190..1abed5b0b --- a/litex/build/xilinx/ise.py +++ b/litex/build/xilinx/ise.py @@ -96,8 +96,8 @@ def _run_yosys(device, sources, vincpaths, build_name): else: raise OSError("Unsupported device") - ys_contents += """hierarchy -top top -synth_xilinx -top top -family {family} -ise + ys_contents += """hierarchy -top {build_name} +synth_xilinx -top {build_name} -family {family} -ise write_edif -pvector bra {build_name}.edif""".format(build_name=build_name, family=family) ys_name = build_name + ".ys" From 9c3663f3d23611d5df97ff0a5fbc1b6010c2befe Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Wed, 29 Jun 2022 11:15:48 +0200 Subject: [PATCH 8/9] test/test_cpu: Re-enable cv32e40p/marocchino. --- test/test_cpu.py | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/test/test_cpu.py b/test/test_cpu.py index b28ae4326..5614d4c43 100644 --- a/test/test_cpu.py +++ b/test/test_cpu.py @@ -36,13 +36,12 @@ class TestCPU(unittest.TestCase): def test_cpu(self): tested_cpus = [ - #"cv32e40p", # (riscv / softcore) + "cv32e40p", # (riscv / softcore) "femtorv", # (riscv / softcore) "firev", # (riscv / softcore) "ibex", # (riscv / softcore) - #"marocchino", # (or1k / softcore) + "marocchino", # (or1k / softcore) "naxriscv", # (riscv / softcore) - #"rocket", # (riscv / softcore) "serv", # (riscv / softcore) "vexriscv", # (riscv / softcore) "vexriscv_smp", # (riscv / softcore) @@ -62,6 +61,7 @@ class TestCPU(unittest.TestCase): "mor1kx", # (or1k / softcore) -> Verilator compilation issue. "neorv32", # (riscv / softcore) -> Requires VHDL->Verilog (GHDL + Yosys). "picorv32", # (riscv / softcore) -> Verilator compilation issue. + "rocket", # (riscv / softcore) -> Not enough RAM in CI. "zynq7000", # (arm / hardcore) -> Hardcore. "zynqmp", # (aarch64 / hardcore) -> Hardcore. ] From 7388684232bad6bfbc2dca8b9e7f557c245d01aa Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Wed, 29 Jun 2022 11:19:21 +0200 Subject: [PATCH 9/9] integration/export/get_memory_x: Replace spi_flash with rom. Even when ROM is stored in SPI Flash, ROM regions has to be created. --- litex/soc/integration/export.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/litex/soc/integration/export.py b/litex/soc/integration/export.py index b9def3137..3fae21e44 100644 --- a/litex/soc/integration/export.py +++ b/litex/soc/integration/export.py @@ -603,8 +603,8 @@ def get_csr_svd(soc, vendor="litex", name="soc", description=None): def get_memory_x(soc): r = get_linker_regions(soc.mem_regions) r += '\n' - r += 'REGION_ALIAS("REGION_TEXT", spiflash);\n' - r += 'REGION_ALIAS("REGION_RODATA", spiflash);\n' + r += 'REGION_ALIAS("REGION_TEXT", rom);\n' + r += 'REGION_ALIAS("REGION_RODATA", rom);\n' r += 'REGION_ALIAS("REGION_DATA", sram);\n' r += 'REGION_ALIAS("REGION_BSS", sram);\n' r += 'REGION_ALIAS("REGION_HEAP", sram);\n'