From dc78c3f47b2edb0fd2e26410ebb213f0b76ef426 Mon Sep 17 00:00:00 2001
From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Thu, 4 Apr 2024 13:02:17 +0200
Subject: [PATCH] soc/interconnect/stream/ClockDomainCrossing: Add a Buffer
 when same Clk Domains when buffered=True.

---
 litex/soc/interconnect/stream.py | 12 ++++++++++--
 1 file changed, 10 insertions(+), 2 deletions(-)

diff --git a/litex/soc/interconnect/stream.py b/litex/soc/interconnect/stream.py
index c7d521221..2a95d9baa 100644
--- a/litex/soc/interconnect/stream.py
+++ b/litex/soc/interconnect/stream.py
@@ -254,8 +254,16 @@ class ClockDomainCrossing(LiteXModule, DUID):
 
         # Same Clk Domains.
         if cd_from == cd_to:
-            # No adaptation.
-            self.comb += self.sink.connect(self.source)
+            if buffered:
+                # Add Buffer.
+                self.buffer = ClockDomainsRenamer(cd_from)(Buffer(layout))
+                self.comb += [
+                    self.sink.connect(self.buffer.sink),
+                    self.buffer.source.connect(self.source),
+                ]
+            else:
+                # No adaptation.
+                self.comb += self.sink.connect(self.source)
         # Different Clk Domains.
         else:
             if with_common_rst: