diff --git a/migen/fhdl/specials.py b/migen/fhdl/specials.py index f65beb7ab..768f55e4b 100644 --- a/migen/fhdl/specials.py +++ b/migen/fhdl/specials.py @@ -48,7 +48,7 @@ class Tristate(Special): yield self, attr, target_context @staticmethod - def emit_verilog(tristate, ns, fdict): + def emit_verilog(tristate, ns): def pe(e): return verilog_printexpr(ns, e)[0] w, s = value_bits_sign(tristate.target) @@ -58,7 +58,7 @@ class Tristate(Special): if tristate.i is not None: r += "assign " + pe(tristate.i) + " = " + pe(tristate.target) + ";\n" r += "\n" - return r, fdict + return r class TSTriple: def __init__(self, bits_sign=None, min=None, max=None, reset_o=0, reset_oe=0): @@ -123,7 +123,7 @@ class Instance(Special): yield item, "expr", SPECIAL_INOUT @staticmethod - def emit_verilog(instance, ns, fdict): + def emit_verilog(instance, ns): r = instance.of + " " parameters = list(filter(lambda i: isinstance(i, Instance.Parameter), instance.items)) if parameters: @@ -165,7 +165,7 @@ class Instance(Special): r += ")" + synthesis_directive + ";\n\n" else: r += ");\n\n" - return r, fdict + return r (READ_FIRST, WRITE_FIRST, NO_CHANGE) = range(3) @@ -198,8 +198,8 @@ class _MemoryPort(Special): yield self, attr, target_context @staticmethod - def emit_verilog(port, ns, fdict): - return "", fdict # done by parent Memory object + def emit_verilog(port, ns): + return "" # done by parent Memory object class Memory(Special): def __init__(self, width, depth, init=None, name=None): @@ -237,7 +237,7 @@ class Memory(Special): return mp @staticmethod - def emit_verilog(memory, ns, fdict): + def emit_verilog(memory, ns): r = "" def gn(e): if isinstance(e, Memory): @@ -320,7 +320,8 @@ class Memory(Special): r += "$readmemh(\"" + memory_filename + "\", " + gn(memory) + ");\n" r += "end\n\n" - return r, fdict + + return r class SynthesisDirective(Special): def __init__(self, template, **signals): @@ -329,7 +330,7 @@ class SynthesisDirective(Special): self.signals = signals @staticmethod - def emit_verilog(directive, ns, fdict): + def emit_verilog(directive, ns): name_dict = dict((k, ns.get_name(sig)) for k, sig in directive.signals.items()) formatted = directive.template.format(**name_dict) - return "// synthesis " + formatted + "\n", fdict + return "// synthesis " + formatted + "\n" diff --git a/migen/fhdl/verilog.py b/migen/fhdl/verilog.py index 499c74e3f..fbebe8f56 100644 --- a/migen/fhdl/verilog.py +++ b/migen/fhdl/verilog.py @@ -1,6 +1,5 @@ from functools import partial from operator import itemgetter -from collections import OrderedDict from migen.fhdl.structure import * from migen.fhdl.structure import _Operator, _Slice, _Assign, _Fragment @@ -258,14 +257,14 @@ def _lower_specials(overrides, specials): f.specials -= lowered_specials2 return f, lowered_specials -def _printspecials(overrides, specials, ns, fdict): +def _printspecials(overrides, specials, ns): r = "" for special in sorted(specials, key=lambda x: x.huid): - pr, fdict = _call_special_classmethod(overrides, special, "emit_verilog", ns, fdict) + pr = _call_special_classmethod(overrides, special, "emit_verilog", ns) if pr is None: raise NotImplementedError("Special " + str(special) + " failed to implement emit_verilog") r += pr - return r, fdict + return r class VerilogConvert: def __init__(self, f, ios=None, name="top", @@ -312,9 +311,7 @@ class VerilogConvert: r += _printheader(self.f, self.ios, self.name, self.ns) r += _printcomb(self.f, self.ns, self.display_run) r += _printsync(self.f, self.ns) - fdict = OrderedDict() - src, fdict = _printspecials(self.special_overrides, self.f.specials - self.lowered_specials, self.ns, fdict) - r += src + r += _printspecials(self.special_overrides, self.f.specials - self.lowered_specials, self.ns) r += "endmodule\n" return r