From dcc881db924370d8aba828e7a3a4990211723eb7 Mon Sep 17 00:00:00 2001 From: Benjamin Herrenschmidt Date: Tue, 12 May 2020 20:58:19 +1000 Subject: [PATCH] soc: Don't create a share intercon with only one master and one slave This creates a lot of useless churn in the resulting verilog. Instead use a point to point interconnect in that case. Signed-off-by: Benjamin Herrenschmidt --- litex/soc/integration/soc.py | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/litex/soc/integration/soc.py b/litex/soc/integration/soc.py index b2e492968..42366b6c1 100644 --- a/litex/soc/integration/soc.py +++ b/litex/soc/integration/soc.py @@ -824,7 +824,14 @@ class SoC(Module): # SoC Bus Interconnect --------------------------------------------------------------------- bus_masters = self.bus.masters.values() bus_slaves = [(self.bus.regions[n].decoder(self.bus), s) for n, s in self.bus.slaves.items()] - if len(bus_masters) and len(bus_slaves): + # One master and one slave, use a point to point interconnect, this is useful for + # generating standalone components such as LiteDRAM whose external control + # interface is a wishbone. + if len(bus_masters) == 1 and len(bus_slaves) == 1: + self.submodules.bus_interconnect = wishbone.InterconnectPointToPoint( + master = list(bus_masters)[0], + slave = list(self.bus.slaves.values())[0]) + elif len(bus_masters) and len(bus_slaves): self.submodules.bus_interconnect = wishbone.InterconnectShared( masters = bus_masters, slaves = bus_slaves,