From dd72b1acfe8f817693aa414a0398d91edfb2cb90 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Mon, 17 May 2021 09:53:40 +0200 Subject: [PATCH] soc/add_cpu: Add **kwargs support. --- litex/soc/integration/soc.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/litex/soc/integration/soc.py b/litex/soc/integration/soc.py index f0dba753f..cf6d53061 100644 --- a/litex/soc/integration/soc.py +++ b/litex/soc/integration/soc.py @@ -861,7 +861,7 @@ class SoC(Module): self.add_config("CSR_DATA_WIDTH", self.csr.data_width) self.add_config("CSR_ALIGNMENT", self.csr.alignment) - def add_cpu(self, name="vexriscv", variant="standard", cls=None, reset_address=None): + def add_cpu(self, name="vexriscv", variant="standard", cls=None, reset_address=None, **kwargs): # Check that CPU is supported. if name not in cpu.CPUS.keys(): self.logger.error("{} CPU {}, supporteds: {}.".format( @@ -884,7 +884,7 @@ class SoC(Module): colorer(", ".join(cpu_cls.variants)))) raise self.check_if_exists("cpu") - self.submodules.cpu = cpu_cls(self.platform, variant) + self.submodules.cpu = cpu_cls(self.platform, variant, **kwargs) # Update SoC with CPU constraints. for n, (origin, size) in enumerate(self.cpu.io_regions.items()):