diff --git a/litex/boards/platforms/arty.py b/litex/boards/platforms/arty.py
index f79b21460..c996cff29 100644
--- a/litex/boards/platforms/arty.py
+++ b/litex/boards/platforms/arty.py
@@ -109,8 +109,12 @@ _io = [
             "V4 T5 U4 V5 V1 T3 U3 R3"),
             IOStandard("SSTL135"),
             Misc("IN_TERM=UNTUNED_SPLIT_40")),
-        Subsignal("dqs_p", Pins("N2 U2"), IOStandard("DIFF_SSTL135")),
-        Subsignal("dqs_n", Pins("N1 V2"), IOStandard("DIFF_SSTL135")),
+        Subsignal("dqs_p", Pins("N2 U2"),
+            IOStandard("DIFF_SSTL135"),
+            Misc("IN_TERM=UNTUNED_SPLIT_40")),
+        Subsignal("dqs_n", Pins("N1 V2"),
+            IOStandard("DIFF_SSTL135"),
+            Misc("IN_TERM=UNTUNED_SPLIT_40")),
         Subsignal("clk_p", Pins("U9"), IOStandard("DIFF_SSTL135")),
         Subsignal("clk_n", Pins("V9"), IOStandard("DIFF_SSTL135")),
         Subsignal("cke", Pins("N5"), IOStandard("SSTL135")),
diff --git a/litex/boards/targets/arty.py b/litex/boards/targets/arty.py
index 8b0840e46..b7f36b30e 100755
--- a/litex/boards/targets/arty.py
+++ b/litex/boards/targets/arty.py
@@ -27,6 +27,7 @@ from liteeth.frontend.etherbone import LiteEthEtherbone
 class _CRG(Module):
     def __init__(self, platform, sys_clk_freq):
         self.clock_domains.cd_sys       = ClockDomain()
+        self.clock_domains.cd_sys2x     = ClockDomain(reset_less=True)
         self.clock_domains.cd_sys4x     = ClockDomain(reset_less=True)
         self.clock_domains.cd_sys4x_dqs = ClockDomain(reset_less=True)
         self.clock_domains.cd_clk200    = ClockDomain()
@@ -38,6 +39,7 @@ class _CRG(Module):
         self.comb += pll.reset.eq(~platform.request("cpu_reset"))
         pll.register_clkin(platform.request("clk100"), 100e6)
         pll.create_clkout(self.cd_sys,       sys_clk_freq)
+        pll.create_clkout(self.cd_sys2x,     2*sys_clk_freq)
         pll.create_clkout(self.cd_sys4x,     4*sys_clk_freq)
         pll.create_clkout(self.cd_sys4x_dqs, 4*sys_clk_freq, phase=90)
         pll.create_clkout(self.cd_clk200,    200e6)
@@ -62,9 +64,10 @@ class BaseSoC(SoCSDRAM):
         # DDR3 SDRAM -------------------------------------------------------------------------------
         if not self.integrated_main_ram_size:
             self.submodules.ddrphy = s7ddrphy.A7DDRPHY(platform.request("ddram"),
-                memtype      = "DDR3",
-                nphases      = 4,
-                sys_clk_freq = sys_clk_freq)
+                memtype        = "DDR3",
+                nphases        = 4,
+                sys_clk_freq   = sys_clk_freq,
+                interface_type = "MEMORY")
             self.add_csr("ddrphy")
             sdram_module = MT41K128M16(sys_clk_freq, "1:4")
             self.register_sdram(self.ddrphy,