From dda7a8c5f34a5c18262dc50924d8e16b2616d61d Mon Sep 17 00:00:00 2001 From: Piotr Esden-Tempski Date: Thu, 12 Mar 2020 22:08:54 -0700 Subject: [PATCH] Split CSR documentation diagrams with more than 8 bits into multiple lanes. In cases when each CSR bit has a name and we use CSR with more than 8 bits, the register diagram quickly becomes crowded and hard to read. With this patch we split the register into multiple lanes of 8 bits each. --- litex/soc/doc/csr.py | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/litex/soc/doc/csr.py b/litex/soc/doc/csr.py index 31b4b8167..0b0670daa 100644 --- a/litex/soc/doc/csr.py +++ b/litex/soc/doc/csr.py @@ -266,7 +266,8 @@ class DocumentedCSRRegion: print(" {\"name\": \"" + reg.short_name.lower() + self.bit_range(reg.offset, reg.offset + reg.size, empty_if_zero=True) + "\", " + attr_str + "\"bits\": " + str(reg.size) + "}" + term, file=stream) if reg.size != self.csr_data_width: print(" {\"bits\": " + str(self.csr_data_width - reg.size) + "},", file=stream) - print(" ], \"config\": {\"hspace\": 400, \"bits\": " + str(self.busword) + ", \"lanes\": 1 }, \"options\": {\"hspace\": 400, \"bits\": " + str(self.busword) + ", \"lanes\": 1}", file=stream) + lanes = self.busword / 8 + print(" ], \"config\": {\"hspace\": 400, \"bits\": " + str(self.busword) + ", \"lanes\": " + str(lanes) + " }, \"options\": {\"hspace\": 400, \"bits\": " + str(self.busword) + ", \"lanes\": " + str(lanes) + "}", file=stream) print(" }", file=stream) print("", file=stream)