From de287609132cd026a7ca4d94ba631d045e02a1e9 Mon Sep 17 00:00:00 2001
From: Sebastien Bourdeauducq <sebastien@milkymist.org>
Date: Sat, 7 Jul 2012 00:11:58 +0200
Subject: [PATCH] tb/framebuffer: compute parameters

---
 tb/framebuffer/framebuffer.py | 24 ++++++++++++++----------
 1 file changed, 14 insertions(+), 10 deletions(-)

diff --git a/tb/framebuffer/framebuffer.py b/tb/framebuffer/framebuffer.py
index b12cf679f..65b780ad6 100644
--- a/tb/framebuffer/framebuffer.py
+++ b/tb/framebuffer/framebuffer.py
@@ -18,17 +18,21 @@ def main():
 	sim.run(1)
 	def csr_w(addr, d):
 		sim.wr(dut.bank.description[addr].field.storage, d)
-	csr_w(1, 2) # hres
-	csr_w(2, 3) # hsync_start
-	csr_w(3, 4) # hsync_stop
-	csr_w(4, 5) # hscan
-	csr_w(5, 2) # vres
-	csr_w(6, 3) # vsync_start
-	csr_w(7, 4) # vsync_stop
-	csr_w(8, 5) # vscan
-	csr_w(10, 2*2*4) # length
+		
+	hres = 4
+	vres = 4
+	
+	csr_w(1, hres) # hres
+	csr_w(2, hres+3) # hsync_start
+	csr_w(3, hres+5) # hsync_stop
+	csr_w(4, hres+10) # hscan
+	csr_w(5, vres) # vres
+	csr_w(6, vres+3) # vsync_start
+	csr_w(7, vres+5) # vsync_stop
+	csr_w(8, vres+10) # vscan
+	csr_w(10, hres*vres*4) # length
 	csr_w(0, 1) # enable
 	
-	sim.run(200)
+	sim.run(1000)
 
 main()