From de698c51e48f71db11edaf2766eb5da0a1251bff Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Mon, 2 Mar 2015 11:21:13 +0100 Subject: [PATCH] sdram: rename self.phy_settings to self.settings (using phy.settings instead of phy.phy_settings seems cleaner) --- misoclib/mem/sdram/lasmicon/__init__.py | 22 ++++++++-------- misoclib/mem/sdram/lasmicon/multiplexer.py | 24 ++++++++--------- misoclib/mem/sdram/minicon/__init__.py | 20 +++++++-------- misoclib/mem/sdram/phy/gensdrphy.py | 2 +- misoclib/mem/sdram/phy/initsequence.py | 30 +++++++++++----------- misoclib/mem/sdram/phy/k7ddrphy.py | 8 +++--- misoclib/mem/sdram/phy/s6ddrphy.py | 14 +++++----- misoclib/mem/sdram/test/minicon_tb.py | 4 +-- misoclib/soc/sdram.py | 10 ++++---- targets/de0nano.py | 2 +- targets/kc705.py | 2 +- targets/mlabs_video.py | 2 +- targets/pipistrello.py | 2 +- targets/ppro.py | 2 +- 14 files changed, 72 insertions(+), 72 deletions(-) diff --git a/misoclib/mem/sdram/lasmicon/__init__.py b/misoclib/mem/sdram/lasmicon/__init__.py index d0cf991c9..94735d5b2 100644 --- a/misoclib/mem/sdram/lasmicon/__init__.py +++ b/misoclib/mem/sdram/lasmicon/__init__.py @@ -6,24 +6,24 @@ from misoclib.mem.sdram.lasmicon.bankmachine import * from misoclib.mem.sdram.lasmicon.multiplexer import * class LASMIcon(Module): - def __init__(self, phy_settings, geom_settings, timing_settings): - if phy_settings.memtype in ["SDR"]: - burst_length = phy_settings.nphases*1 # command multiplication*SDR - elif phy_settings.memtype in ["DDR", "LPDDR", "DDR2", "DDR3"]: - burst_length = phy_settings.nphases*2 # command multiplication*DDR + def __init__(self, phy, geom_settings, timing_settings): + if phy.settings.memtype in ["SDR"]: + burst_length = phy.settings.nphases*1 # command multiplication*SDR + elif phy.settings.memtype in ["DDR", "LPDDR", "DDR2", "DDR3"]: + burst_length = phy.settings.nphases*2 # command multiplication*DDR address_align = log2_int(burst_length) self.dfi = dfi.Interface(geom_settings.mux_a, geom_settings.bank_a, - phy_settings.dfi_d, - phy_settings.nphases) + phy.settings.dfi_d, + phy.settings.nphases) self.lasmic = lasmibus.Interface( aw=geom_settings.row_a + geom_settings.col_a - address_align, - dw=phy_settings.dfi_d*phy_settings.nphases, + dw=phy.settings.dfi_d*phy.settings.nphases, nbanks=2**geom_settings.bank_a, req_queue_size=timing_settings.req_queue_size, - read_latency=phy_settings.read_latency+1, - write_latency=phy_settings.write_latency+1) + read_latency=phy.settings.read_latency+1, + write_latency=phy.settings.write_latency+1) self.nrowbits = geom_settings.col_a - address_align ### @@ -33,7 +33,7 @@ class LASMIcon(Module): self.submodules.bank_machines = [BankMachine(geom_settings, timing_settings, address_align, i, getattr(self.lasmic, "bank"+str(i))) for i in range(2**geom_settings.bank_a)] - self.submodules.multiplexer = Multiplexer(phy_settings, geom_settings, timing_settings, + self.submodules.multiplexer = Multiplexer(phy, geom_settings, timing_settings, self.bank_machines, self.refresher, self.dfi, self.lasmic) diff --git a/misoclib/mem/sdram/lasmicon/multiplexer.py b/misoclib/mem/sdram/lasmicon/multiplexer.py index c7cd69541..3f977efb6 100644 --- a/misoclib/mem/sdram/lasmicon/multiplexer.py +++ b/misoclib/mem/sdram/lasmicon/multiplexer.py @@ -89,8 +89,8 @@ class _Steerer(Module): ] class Multiplexer(Module, AutoCSR): - def __init__(self, phy_settings, geom_settings, timing_settings, bank_machines, refresher, dfi, lasmic): - assert(phy_settings.nphases == len(dfi.phases)) + def __init__(self, phy, geom_settings, timing_settings, bank_machines, refresher, dfi, lasmic): + assert(phy.settings.nphases == len(dfi.phases)) # Command choosing requests = [bm.cmd for bm in bank_machines] @@ -100,7 +100,7 @@ class Multiplexer(Module, AutoCSR): choose_cmd.want_reads.eq(0), choose_cmd.want_writes.eq(0) ] - if phy_settings.nphases == 1: + if phy.settings.nphases == 1: self.comb += [ choose_cmd.want_cmds.eq(1), choose_req.want_cmds.eq(1) @@ -159,19 +159,19 @@ class Multiplexer(Module, AutoCSR): fsm = FSM() self.submodules += fsm - def steerer_sel(steerer, phy_settings, r_w_n): + def steerer_sel(steerer, phy, r_w_n): r = [] - for i in range(phy_settings.nphases): + for i in range(phy.settings.nphases): s = steerer.sel[i].eq(STEER_NOP) if r_w_n == "read": - if i == phy_settings.rdphase: + if i == phy.settings.rdphase: s = steerer.sel[i].eq(STEER_REQ) - elif i == phy_settings.rdcmdphase: + elif i == phy.settings.rdcmdphase: s = steerer.sel[i].eq(STEER_CMD) elif r_w_n == "write": - if i == phy_settings.wrphase: + if i == phy.settings.wrphase: s = steerer.sel[i].eq(STEER_REQ) - elif i == phy_settings.wrcmdphase: + elif i == phy.settings.wrcmdphase: s = steerer.sel[i].eq(STEER_CMD) else: raise ValueError @@ -183,7 +183,7 @@ class Multiplexer(Module, AutoCSR): choose_req.want_reads.eq(1), choose_cmd.cmd.ack.eq(1), choose_req.cmd.ack.eq(1), - steerer_sel(steerer, phy_settings, "read"), + steerer_sel(steerer, phy, "read"), If(write_available, # TODO: switch only after several cycles of ~read_available? If(~read_available | max_read_time, NextState("RTW")) @@ -195,7 +195,7 @@ class Multiplexer(Module, AutoCSR): choose_req.want_writes.eq(1), choose_cmd.cmd.ack.eq(1), choose_req.cmd.ack.eq(1), - steerer_sel(steerer, phy_settings, "write"), + steerer_sel(steerer, phy, "write"), If(read_available, If(~write_available | max_write_time, NextState("WTR")) ), @@ -205,7 +205,7 @@ class Multiplexer(Module, AutoCSR): steerer.sel[0].eq(STEER_REFRESH), If(~refresher.req, NextState("READ")) ) - fsm.delayed_enter("RTW", "WRITE", phy_settings.read_latency-1) # FIXME: reduce this, actual limit is around (cl+1)/nphases + fsm.delayed_enter("RTW", "WRITE", phy.settings.read_latency-1) # FIXME: reduce this, actual limit is around (cl+1)/nphases fsm.delayed_enter("WTR", "READ", timing_settings.tWTR-1) # FIXME: workaround for zero-delay loop simulation problem with Icarus Verilog fsm.finalize() diff --git a/misoclib/mem/sdram/minicon/__init__.py b/misoclib/mem/sdram/minicon/__init__.py index 1f7660eeb..c03f93d46 100644 --- a/misoclib/mem/sdram/minicon/__init__.py +++ b/misoclib/mem/sdram/minicon/__init__.py @@ -35,26 +35,26 @@ class _AddressSlicer: return Cat(Replicate(0, self.address_align), address[:split]) class Minicon(Module): - def __init__(self, phy_settings, geom_settings, timing_settings): - if phy_settings.memtype in ["SDR"]: - burst_length = phy_settings.nphases*1 # command multiplication*SDR - elif phy_settings.memtype in ["DDR", "LPDDR", "DDR2", "DDR3"]: - burst_length = phy_settings.nphases*2 # command multiplication*DDR + def __init__(self, phy, geom_settings, timing_settings): + if phy.settings.memtype in ["SDR"]: + burst_length = phy.settings.nphases*1 # command multiplication*SDR + elif phy.settings.memtype in ["DDR", "LPDDR", "DDR2", "DDR3"]: + burst_length = phy.settings.nphases*2 # command multiplication*DDR address_align = log2_int(burst_length) nbanks = range(2**geom_settings.bank_a) A10_ENABLED = 0 COLUMN = 1 ROW = 2 - rdphase = phy_settings.rdphase - wrphase = phy_settings.wrphase + rdphase = phy.settings.rdphase + wrphase = phy.settings.wrphase self.dfi = dfi = dfibus.Interface(geom_settings.mux_a, geom_settings.bank_a, - phy_settings.dfi_d, - phy_settings.nphases) + phy.settings.dfi_d, + phy.settings.nphases) - self.bus = bus = wishbone.Interface(data_width=phy_settings.nphases*flen(dfi.phases[rdphase].rddata)) + self.bus = bus = wishbone.Interface(data_width=phy.settings.nphases*flen(dfi.phases[rdphase].rddata)) slicer = _AddressSlicer(geom_settings.col_a, geom_settings.bank_a, geom_settings.row_a, address_align) refresh_req = Signal() refresh_ack = Signal() diff --git a/misoclib/mem/sdram/phy/gensdrphy.py b/misoclib/mem/sdram/phy/gensdrphy.py index 8dbba501c..f7af68d40 100644 --- a/misoclib/mem/sdram/phy/gensdrphy.py +++ b/misoclib/mem/sdram/phy/gensdrphy.py @@ -34,7 +34,7 @@ class GENSDRPHY(Module): ba = flen(pads.ba) d = flen(pads.dq) - self.phy_settings = sdram.PhySettings( + self.settings = sdram.PhySettings( memtype="SDR", dfi_d=d, nphases=1, diff --git a/misoclib/mem/sdram/phy/initsequence.py b/misoclib/mem/sdram/phy/initsequence.py index 32ccd77f1..3dc561d97 100644 --- a/misoclib/mem/sdram/phy/initsequence.py +++ b/misoclib/mem/sdram/phy/initsequence.py @@ -4,7 +4,7 @@ def get_sdram_phy_header(sdram_phy): r = "#ifndef __GENERATED_SDRAM_PHY_H\n#define __GENERATED_SDRAM_PHY_H\n" r += "#include \n#include \n#include \n\n" - nphases = sdram_phy.phy_settings.nphases + nphases = sdram_phy.settings.nphases r += "#define DFII_NPHASES "+str(nphases)+"\n\n" r += "static void cdelay(int i);\n" @@ -29,7 +29,7 @@ static void command_p{n}(int cmd) #define command_prd(X) command_p{rdphase}(X) #define command_pwr(X) command_p{wrphase}(X) -""".format(rdphase=str(sdram_phy.phy_settings.rdphase), wrphase=str(sdram_phy.phy_settings.wrphase)) +""".format(rdphase=str(sdram_phy.settings.rdphase), wrphase=str(sdram_phy.settings.wrphase)) r +="\n" # @@ -64,10 +64,10 @@ const unsigned int dfii_pix_rddata_addr[{n}] = {{ "CKE" : "DFII_CONTROL_CKE|DFII_CONTROL_ODT|DFII_CONTROL_RESET_N" } - cl = sdram_phy.phy_settings.cl + cl = sdram_phy.settings.cl - if sdram_phy.phy_settings.memtype == "SDR": - bl = sdram_phy.phy_settings.nphases + if sdram_phy.settings.memtype == "SDR": + bl = sdram_phy.settings.nphases mr = log2_int(bl) + (cl << 4) reset_dll = 1 << 8 @@ -81,8 +81,8 @@ const unsigned int dfii_pix_rddata_addr[{n}] = {{ ("Load Mode Register / CL={0:d}, BL={1:d}".format(cl, bl), mr, 0, cmds["MODE_REGISTER"], 200) ] - elif sdram_phy.phy_settings.memtype == "DDR": - bl = 2*sdram_phy.phy_settings.nphases + elif sdram_phy.settings.memtype == "DDR": + bl = 2*sdram_phy.settings.nphases mr = log2_int(bl) + (cl << 4) emr = 0 reset_dll = 1 << 8 @@ -98,8 +98,8 @@ const unsigned int dfii_pix_rddata_addr[{n}] = {{ ("Load Mode Register / CL={0:d}, BL={1:d}".format(cl, bl), mr, 0, cmds["MODE_REGISTER"], 200) ] - elif sdram_phy.phy_settings.memtype == "LPDDR": - bl = 2*sdram_phy.phy_settings.nphases + elif sdram_phy.settings.memtype == "LPDDR": + bl = 2*sdram_phy.settings.nphases mr = log2_int(bl) + (cl << 4) emr = 0 reset_dll = 1 << 8 @@ -115,8 +115,8 @@ const unsigned int dfii_pix_rddata_addr[{n}] = {{ ("Load Mode Register / CL={0:d}, BL={1:d}".format(cl, bl), mr, 0, cmds["MODE_REGISTER"], 200) ] - elif sdram_phy.phy_settings.memtype == "DDR2": - bl = 2*sdram_phy.phy_settings.nphases + elif sdram_phy.settings.memtype == "DDR2": + bl = 2*sdram_phy.settings.nphases wr = 2 mr = log2_int(bl) + (cl << 4) + (wr << 9) emr = 0 @@ -139,8 +139,8 @@ const unsigned int dfii_pix_rddata_addr[{n}] = {{ ("Load Extended Mode Register / OCD Default", emr+ocd, 1, cmds["MODE_REGISTER"], 0), ("Load Extended Mode Register / OCD Exit", emr, 1, cmds["MODE_REGISTER"], 0), ] - elif sdram_phy.phy_settings.memtype == "DDR3": - bl = 2*sdram_phy.phy_settings.nphases + elif sdram_phy.settings.memtype == "DDR3": + bl = 2*sdram_phy.settings.nphases if bl != 8: raise NotImplementedError("DDR3 PHY header generator only supports BL of 8") @@ -188,7 +188,7 @@ const unsigned int dfii_pix_rddata_addr[{n}] = {{ mr0 = format_mr0(cl, 8, 1) # wr=8 FIXME: this should be ceiling(tWR/tCK) mr1 = format_mr1(1, 1) # Output Drive Strength RZQ/7 (34 ohm) / Rtt RZQ/4 (60 ohm) - mr2 = format_mr2(sdram_phy.phy_settings.cwl, 2) # Rtt(WR) RZQ/4 + mr2 = format_mr2(sdram_phy.settings.cwl, 2) # Rtt(WR) RZQ/4 mr3 = 0 init_sequence = [ @@ -204,7 +204,7 @@ const unsigned int dfii_pix_rddata_addr[{n}] = {{ # the value of MR1 needs to be modified during write leveling r += "#define DDR3_MR1 {}\n\n".format(mr1) else: - raise NotImplementedError("Unsupported memory type: "+sdram_phy.phy_settings.memtype) + raise NotImplementedError("Unsupported memory type: "+sdram_phy.settings.memtype) r += "static void init_sequence(void)\n{\n" for comment, a, ba, cmd, delay in init_sequence: diff --git a/misoclib/mem/sdram/phy/k7ddrphy.py b/misoclib/mem/sdram/phy/k7ddrphy.py index 99ff9417b..420219445 100644 --- a/misoclib/mem/sdram/phy/k7ddrphy.py +++ b/misoclib/mem/sdram/phy/k7ddrphy.py @@ -24,7 +24,7 @@ class K7DDRPHY(Module, AutoCSR): self._wdly_dqs_rst = CSR() self._wdly_dqs_inc = CSR() - self.phy_settings = sdram.PhySettings( + self.settings = sdram.PhySettings( memtype=memtype, dfi_d=2*d, nphases=nphases, @@ -38,7 +38,7 @@ class K7DDRPHY(Module, AutoCSR): write_latency=2 ) - self.dfi = Interface(a, ba, self.phy_settings.dfi_d, nphases) + self.dfi = Interface(a, ba, self.settings.dfi_d, nphases) ### @@ -270,7 +270,7 @@ class K7DDRPHY(Module, AutoCSR): # 2 cycles through OSERDESE2 # 2 cycles CAS # 2 cycles through ISERDESE2 - rddata_en = self.dfi.phases[self.phy_settings.rdphase].rddata_en + rddata_en = self.dfi.phases[self.settings.rdphase].rddata_en for i in range(5): n_rddata_en = Signal() self.sync += n_rddata_en.eq(rddata_en) @@ -280,7 +280,7 @@ class K7DDRPHY(Module, AutoCSR): oe = Signal() last_wrdata_en = Signal(4) - wrphase = self.dfi.phases[self.phy_settings.wrphase] + wrphase = self.dfi.phases[self.settings.wrphase] self.sync += last_wrdata_en.eq(Cat(wrphase.wrdata_en, last_wrdata_en[:3])) self.comb += oe.eq(last_wrdata_en[1] | last_wrdata_en[2] | last_wrdata_en[3]) self.sync += \ diff --git a/misoclib/mem/sdram/phy/s6ddrphy.py b/misoclib/mem/sdram/phy/s6ddrphy.py index f3ed15bcb..1d5fe0f73 100644 --- a/misoclib/mem/sdram/phy/s6ddrphy.py +++ b/misoclib/mem/sdram/phy/s6ddrphy.py @@ -29,7 +29,7 @@ class S6DDRPHY(Module): d = flen(pads.dq) nphases = 2 - self.phy_settings = sdram.PhySettings( + self.settings = sdram.PhySettings( memtype=memtype, dfi_d=2*d, nphases=nphases, @@ -42,7 +42,7 @@ class S6DDRPHY(Module): write_latency=0 ) - self.dfi = Interface(a, ba, self.phy_settings.dfi_d, nphases) + self.dfi = Interface(a, ba, self.settings.dfi_d, nphases) self.clk4x_wr_strb = Signal() self.clk4x_rd_strb = Signal() @@ -337,19 +337,19 @@ class S6DDRPHY(Module): # # DQ/DQS/DM control # - self.comb += drive_dq.eq(d_dfi[self.phy_settings.wrphase].wrdata_en) + self.comb += drive_dq.eq(d_dfi[self.settings.wrphase].wrdata_en) d_dfi_wrdata_en = Signal() - sd_sys += d_dfi_wrdata_en.eq(d_dfi[self.phy_settings.wrphase].wrdata_en) + sd_sys += d_dfi_wrdata_en.eq(d_dfi[self.settings.wrphase].wrdata_en) r_dfi_wrdata_en = Signal(2) sd_sdram_half += r_dfi_wrdata_en.eq(Cat(d_dfi_wrdata_en, r_dfi_wrdata_en[0])) self.comb += drive_dqs.eq(r_dfi_wrdata_en[1]) - rddata_sr = Signal(self.phy_settings.read_latency) - sd_sys += rddata_sr.eq(Cat(rddata_sr[1:self.phy_settings.read_latency], - d_dfi[self.phy_settings.rdphase].rddata_en)) + rddata_sr = Signal(self.settings.read_latency) + sd_sys += rddata_sr.eq(Cat(rddata_sr[1:self.settings.read_latency], + d_dfi[self.settings.rdphase].rddata_en)) for n, phase in enumerate(self.dfi.phases): self.comb += [ diff --git a/misoclib/mem/sdram/test/minicon_tb.py b/misoclib/mem/sdram/test/minicon_tb.py index d13213934..abfb5e035 100644 --- a/misoclib/mem/sdram/test/minicon_tb.py +++ b/misoclib/mem/sdram/test/minicon_tb.py @@ -25,7 +25,7 @@ class MiniconTB(Module): def __init__(self, sdrphy, dfi, sdram_geom, sdram_timing, pads, sdram_clk): self.clk_freq = 80000000 - phy_settings = sdrphy.phy_settings + phy_settings = sdrphy.settings rdphase = phy_settings.rdphase self.submodules.slave = Minicon(phy_settings, sdram_geom, sdram_timing) @@ -70,7 +70,7 @@ class MiniconTB(Module): def gen_simulation(self, selfp): dfi = selfp.dfi phy = self.sdrphy - rdphase = phy.phy_settings.rdphase + rdphase = phy.settings.rdphase cycle = 0 while True: diff --git a/misoclib/soc/sdram.py b/misoclib/soc/sdram.py index 87a59d064..5f49af59a 100644 --- a/misoclib/soc/sdram.py +++ b/misoclib/soc/sdram.py @@ -33,19 +33,19 @@ class SDRAMSoC(SoC): self._sdram_phy_registered = False - def register_sdram_phy(self, phy_dfi, phy_settings, sdram_geom, sdram_timing): + def register_sdram_phy(self, phy, sdram_geom, sdram_timing): if self._sdram_phy_registered: raise FinalizeError self._sdram_phy_registered = True # DFI self.submodules.dfii = dfii.DFIInjector(sdram_geom.mux_a, sdram_geom.bank_a, - phy_settings.dfi_d, phy_settings.nphases) - self.submodules.dficon0 = dfi.Interconnect(self.dfii.master, phy_dfi) + phy.settings.dfi_d, phy.settings.nphases) + self.submodules.dficon0 = dfi.Interconnect(self.dfii.master, phy.dfi) # LASMICON if self.ramcon_type == "lasmicon": - self.submodules.lasmicon = lasmicon.LASMIcon(phy_settings, sdram_geom, sdram_timing) + self.submodules.lasmicon = lasmicon.LASMIcon(phy, sdram_geom, sdram_timing) self.submodules.dficon1 = dfi.Interconnect(self.lasmicon.dfi, self.dfii.slave) self.submodules.lasmixbar = crossbar.Crossbar([self.lasmicon.lasmic], self.lasmicon.nrowbits) @@ -64,7 +64,7 @@ class SDRAMSoC(SoC): if self.with_l2: raise ValueError("MINICON does not implement L2 cache (Use LASMICON or disable L2 cache (with_l2=False))") - self.submodules.minicon = sdramcon = minicon.Minicon(phy_settings, sdram_geom, sdram_timing) + self.submodules.minicon = sdramcon = minicon.Minicon(phy, sdram_geom, sdram_timing) self.submodules.dficon1 = dfi.Interconnect(sdramcon.dfi, self.dfii.slave) sdram_width = flen(sdramcon.bus.dat_r) diff --git a/targets/de0nano.py b/targets/de0nano.py index 62e95fab4..ee4faa5a8 100644 --- a/targets/de0nano.py +++ b/targets/de0nano.py @@ -109,6 +109,6 @@ class BaseSoC(SDRAMSoC): self.submodules.crg = _CRG(platform) self.submodules.sdrphy = gensdrphy.GENSDRPHY(platform.request("sdram")) - self.register_sdram_phy(self.sdrphy.dfi, self.sdrphy.phy_settings, sdram_geom, sdram_timing) + self.register_sdram_phy(self.sdrphy, sdram_geom, sdram_timing) default_subtarget = BaseSoC diff --git a/targets/kc705.py b/targets/kc705.py index 8498d91fe..e1007e9b7 100644 --- a/targets/kc705.py +++ b/targets/kc705.py @@ -98,7 +98,7 @@ class BaseSoC(SDRAMSoC): write_time=16 ) self.submodules.ddrphy = k7ddrphy.K7DDRPHY(platform.request("ddram"), memtype="DDR3") - self.register_sdram_phy(self.ddrphy.dfi, self.ddrphy.phy_settings, sdram_geom, sdram_timing) + self.register_sdram_phy(self.ddrphy, sdram_geom, sdram_timing) # If not in ROM, BIOS is in SPI flash if not self.with_rom: diff --git a/targets/mlabs_video.py b/targets/mlabs_video.py index a32ab88ab..8eafcdcc2 100644 --- a/targets/mlabs_video.py +++ b/targets/mlabs_video.py @@ -57,7 +57,7 @@ class BaseSoC(SDRAMSoC): ) self.submodules.ddrphy = s6ddrphy.S6DDRPHY(platform.request("ddram"), memtype="DDR", rd_bitslip=0, wr_bitslip=3, dqs_ddr_alignment="C1") - self.register_sdram_phy(self.ddrphy.dfi, self.ddrphy.phy_settings, sdram_geom, sdram_timing) + self.register_sdram_phy(self.ddrphy, sdram_geom, sdram_timing) # If not in ROM, BIOS is in // NOR flash if not self.with_rom: diff --git a/targets/pipistrello.py b/targets/pipistrello.py index 3ca47de35..104768b9f 100644 --- a/targets/pipistrello.py +++ b/targets/pipistrello.py @@ -121,7 +121,7 @@ class BaseSoC(SDRAMSoC): platform.add_platform_command(""" PIN "BUFG.O" CLOCK_DEDICATED_ROUTE = FALSE; """) - self.register_sdram_phy(self.ddrphy.dfi, self.ddrphy.phy_settings, sdram_geom, sdram_timing) + self.register_sdram_phy(self.ddrphy, sdram_geom, sdram_timing) # If not in ROM, BIOS is in SPI flash if not self.with_rom: self.submodules.spiflash = spiflash.SpiFlash(platform.request("spiflash4x"), dummy=11, div=2) diff --git a/targets/ppro.py b/targets/ppro.py index d1292a9b2..142d2b4c7 100644 --- a/targets/ppro.py +++ b/targets/ppro.py @@ -90,7 +90,7 @@ class BaseSoC(SDRAMSoC): write_time=16 ) self.submodules.sdrphy = gensdrphy.GENSDRPHY(platform.request("sdram")) - self.register_sdram_phy(self.sdrphy.dfi, self.sdrphy.phy_settings, sdram_geom, sdram_timing) + self.register_sdram_phy(self.sdrphy, sdram_geom, sdram_timing) # If not in ROM, BIOS is in SPI flash if not self.with_rom: