From dfc207aacb32d576e13028e1447d4ab1aafe859d Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Wed, 22 Jul 2015 21:44:53 +0200 Subject: [PATCH] litepcie: use data instead of dat in dma_layout (allow use of migen.actorlib.packet modules on dma dataflow) --- misoclib/com/litepcie/common.py | 2 +- misoclib/com/litepcie/frontend/dma/reader.py | 2 +- misoclib/com/litepcie/frontend/dma/writer.py | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/misoclib/com/litepcie/common.py b/misoclib/com/litepcie/common.py index 4f16c7e68..81f75cb7b 100644 --- a/misoclib/com/litepcie/common.py +++ b/misoclib/com/litepcie/common.py @@ -63,5 +63,5 @@ def interrupt_layout(): def dma_layout(dw): - layout = [("dat", dw)] + layout = [("data", dw)] return EndpointDescription(layout, packetized=True) diff --git a/misoclib/com/litepcie/frontend/dma/reader.py b/misoclib/com/litepcie/frontend/dma/reader.py index c2bbfe2f0..de39e5e8a 100644 --- a/misoclib/com/litepcie/frontend/dma/reader.py +++ b/misoclib/com/litepcie/frontend/dma/reader.py @@ -70,7 +70,7 @@ class DMAReader(Module, AutoCSR): self.comb += [ fifo.sink.stb.eq(port.sink.stb), fifo.sink.sop.eq(port.sink.sop & (port.sink.user_id != last_user_id)), - fifo.sink.dat.eq(port.sink.dat), + fifo.sink.data.eq(port.sink.dat), port.sink.ack.eq(fifo.sink.ack | ~enable), ] self.comb += Record.connect(fifo.source, self.source) diff --git a/misoclib/com/litepcie/frontend/dma/writer.py b/misoclib/com/litepcie/frontend/dma/writer.py index 0522398e4..2f6131d0e 100644 --- a/misoclib/com/litepcie/frontend/dma/writer.py +++ b/misoclib/com/litepcie/frontend/dma/writer.py @@ -28,7 +28,7 @@ class DMAWriter(Module, AutoCSR): self.comb += [ fifo.we.eq(sink.stb & enable), sink.ack.eq(fifo.writable & sink.stb & enable), - fifo.din.eq(sink.dat), + fifo.din.eq(sink.data), fifo.reset.eq(~enable) ]