From e0352a1f0f827a8f086a49b992e963adcdd256d8 Mon Sep 17 00:00:00 2001 From: developandplay <34752929+developandplay@users.noreply.github.com> Date: Wed, 9 Jun 2021 03:36:32 +0200 Subject: [PATCH] Sync ROM_BOOT_ADDRESS with main_ram location Rocket and Blackparrot main_ram starts at 0x80000000 Vexriscv main_ram starts at 0x40000000 --- litex/tools/litex_sim.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/litex/tools/litex_sim.py b/litex/tools/litex_sim.py index f415088c0..c08da56e5 100755 --- a/litex/tools/litex_sim.py +++ b/litex/tools/litex_sim.py @@ -430,7 +430,7 @@ def main(): sdram_init = [] if args.sdram_init is None else get_mem_data(args.sdram_init, cpu.endianness), **soc_kwargs) if args.ram_init is not None or args.sdram_init is not None: - soc.add_constant("ROM_BOOT_ADDRESS", 0x40000000) + soc.add_constant("ROM_BOOT_ADDRESS", soc.mem_map["main_ram"]) if args.with_ethernet: for i in range(4): soc.add_constant("LOCALIP{}".format(i+1), int(args.local_ip.split(".")[i]))