From e15e115170a5ade689138cef5db30229212b8b20 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Mon, 20 Feb 2023 10:47:09 +0100 Subject: [PATCH] cpu/rocket: Add initial dcache/icache/dtlb/itlb configs for .dts generation. Hardwired and probably incorrect, will need to be checked/fixed. --- litex/soc/cores/cpu/rocket/core.py | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/litex/soc/cores/cpu/rocket/core.py b/litex/soc/cores/cpu/rocket/core.py index 342dea849..ad520a2b5 100644 --- a/litex/soc/cores/cpu/rocket/core.py +++ b/litex/soc/cores/cpu/rocket/core.py @@ -369,6 +369,22 @@ class Rocket(CPU): soc.add_config("CPU_COUNT", num_cores) soc.add_config("CPU_ISA", self.get_arch(self.variant)) + # Constants for Cache so we can add them in the DTS. + soc.add_config("CPU_DCACHE_SIZE", 4096) # CHECKME: correct/hardwired? + soc.add_config("CPU_DCACHE_WAYS", 2) # CHECKME: correct/hardwired? + soc.add_config("CPU_DCACHE_BLOCK_SIZE", 64) # CHECKME: correct/hardwired? + + soc.add_config("CPU_ICACHE_SIZE", 4096) # CHECKME: correct/hardwired? + soc.add_config("CPU_ICACHE_WAYS", 2) # CHECKME: correct/hardwired? + soc.add_config("CPU_ICACHE_BLOCK_SIZE", 64) # CHECKME: correct/hardwired? + + # Constants for TLB so we can add them in the DTS. + soc.add_config("CPU_DTLB_SIZE", 4) # CHECKME: correct/hardwired? + soc.add_config("CPU_DTLB_WAYS", 1) # CHECKME: correct/hardwired? + + soc.add_config("CPU_ITLB_SIZE", 4) # CHECKME: correct/hardwired? + soc.add_config("CPU_ITLB_WAYS", 1) # CHECKME: correct/hardwired? + def do_finalize(self): assert hasattr(self, "reset_address") self.specials += Instance("ExampleRocketSystem", **self.cpu_params)