From e18e403f1098ae6d4a51ade5f9e906e5230fffa7 Mon Sep 17 00:00:00 2001
From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Mon, 9 Feb 2015 12:57:05 +0100
Subject: [PATCH] mac: add interpacket gap inserter/checker

---
 liteeth/common.py            |  1 +
 liteeth/mac/__init__.py      |  2 +-
 liteeth/mac/core/__init__.py | 10 +++++++++-
 liteeth/mac/core/gap.py      | 25 +++++++++++++++++++++++++
 4 files changed, 36 insertions(+), 2 deletions(-)
 create mode 100644 liteeth/mac/core/gap.py

diff --git a/liteeth/common.py b/liteeth/common.py
index ec90bf0a9..b94ce2175 100644
--- a/liteeth/common.py
+++ b/liteeth/common.py
@@ -15,6 +15,7 @@ from migen.bank.description import *
 
 eth_mtu = 1532
 eth_min_len = 46
+eth_interpacket_gap = 12
 eth_preamble = 0xD555555555555555
 buffer_depth = 2**log2_int(eth_mtu, need_pow2=False)
 
diff --git a/liteeth/mac/__init__.py b/liteeth/mac/__init__.py
index 10a090f3a..2b9cfb638 100644
--- a/liteeth/mac/__init__.py
+++ b/liteeth/mac/__init__.py
@@ -22,7 +22,7 @@ class LiteEthMACPacketizer(LiteEthPacketizer):
 			mac_header_len)
 
 class LiteEthMAC(Module, AutoCSR):
-	def __init__(self, phy, dw, interface="crossbar", endianness="be",
+	def __init__(self, phy, dw, interface="crossbar", endianness="big",
 			with_hw_preamble_crc=True):
 		self.submodules.core = LiteEthMACCore(phy, dw, endianness, with_hw_preamble_crc)
 		self.csrs = []
diff --git a/liteeth/mac/core/__init__.py b/liteeth/mac/core/__init__.py
index f887c6119..5db1feac7 100644
--- a/liteeth/mac/core/__init__.py
+++ b/liteeth/mac/core/__init__.py
@@ -1,5 +1,5 @@
 from liteeth.common import *
-from liteeth.mac.core import preamble, crc, last_be
+from liteeth.mac.core import gap, preamble, crc, last_be
 
 class LiteEthMACCore(Module, AutoCSR):
 	def __init__(self, phy, dw, endianness="big", with_hw_preamble_crc=True):
@@ -9,6 +9,14 @@ class LiteEthMACCore(Module, AutoCSR):
 		rx_pipeline = [phy]
 		tx_pipeline = [phy]
 
+		# Interpacket gap
+		tx_gap_inserter = gap.LiteEthMACGap(phy.dw)
+		rx_gap_checker = gap.LiteEthMACGap(phy.dw, ack_on_gap=True)
+		self.submodules += tx_gap_inserter, rx_gap_checker
+
+		tx_pipeline += [tx_gap_inserter]
+		rx_pipeline += [rx_gap_checker]
+
 		# Preamble / CRC
 		if with_hw_preamble_crc:
 			self._hw_preamble_crc = CSRStatus(reset=1)
diff --git a/liteeth/mac/core/gap.py b/liteeth/mac/core/gap.py
new file mode 100644
index 000000000..0f1ddd791
--- /dev/null
+++ b/liteeth/mac/core/gap.py
@@ -0,0 +1,25 @@
+from liteeth.common import *
+
+class LiteEthMACGap(Module):
+	def __init__(self, dw, ack_on_gap=False):
+		self.sink = sink = Sink(eth_phy_description(dw))
+		self.source = source = Source(eth_phy_description(dw))
+		###
+		gap = math.ceil(eth_interpacket_gap/(dw//8))
+		self.submodules.counter = counter = Counter(max=gap)
+
+		self.submodules.fsm = fsm = FSM(reset_state="COPY")
+		fsm.act("COPY",
+			counter.reset.eq(1),
+			Record.connect(sink, source),
+			If(sink.stb & sink.eop & sink.ack,
+				NextState("GAP")
+			)
+		)
+		fsm.act("GAP",
+			counter.ce.eq(1),
+			sink.ack.eq(int(ack_on_gap)),
+			If(counter.value == (gap-1),
+				NextState("COPY")
+			)
+		)