diff --git a/litex/soc/cores/cpu/vexriscv/core.py b/litex/soc/cores/cpu/vexriscv/core.py
index 9b363d6c8..af1d90a50 100644
--- a/litex/soc/cores/cpu/vexriscv/core.py
+++ b/litex/soc/cores/cpu/vexriscv/core.py
@@ -135,6 +135,7 @@ class VexRiscv(CPU, AutoCSR):
 
         # # #
 
+        # CPU Instance.
         self.cpu_params = dict(
             i_clk                    = ClockSignal("sys"),
             i_reset                  = ResetSignal("sys") | self.reset,
@@ -168,9 +169,11 @@ class VexRiscv(CPU, AutoCSR):
             i_dBusWishbone_ERR      = dbus.err
         )
 
+        # Add Timer (Optional).
         if with_timer:
             self.add_timer()
 
+        # Add Debug (Optional).
         if "debug" in variant:
             self.add_debug()
 
@@ -332,15 +335,24 @@ class VexRiscv(CPU, AutoCSR):
         platform.add_source(os.path.join(vdir, cpu_filename))
 
     def add_soc_components(self, soc, soc_region_cls):
+        # Connect Debug interface to SoC.
         if "debug" in self.variant:
-            soc.bus.add_slave("vexriscv_debug", self.debug_bus, region=soc_region_cls(
-                origin=soc.mem_map.get("vexriscv_debug"), size=0x100, cached=False))
+            soc.bus.add_slave("vexriscv_debug", self.debug_bus, region=
+                soc_region_cls(
+                    origin = soc.mem_map.get("vexriscv_debug"),
+                    size   = 0x100,
+                    cached = False
+                )
+            )
 
+        # Pass I/D Caches info to software.
         base_variant = str(self.variant.split('+')[0])
-        if base_variant == "lite" or base_variant == "minimal":
-            soc.add_config("CPU_NO_DCACHE")
-        if base_variant == "minimal":
-            soc.add_config("CPU_NO_ICACHE")
+        # DCACHE is present on all variants except minimal and lite.
+        if not base_variant in ["minimal", "lite"]:
+            soc.add_config("CPU_HAS_DCACHE")
+        # ICACHE is present on all variants except minimal.
+        if not base_variant in ["minimal"]:
+            soc.add_config("CPU_HAS_ICACHE")
 
     def use_external_variant(self, variant_filename):
         self.external_variant = True
diff --git a/litex/soc/cores/cpu/vexriscv/system.h b/litex/soc/cores/cpu/vexriscv/system.h
index c48a9ba27..419180245 100644
--- a/litex/soc/cores/cpu/vexriscv/system.h
+++ b/litex/soc/cores/cpu/vexriscv/system.h
@@ -11,9 +11,7 @@ extern "C" {
 
 __attribute__((unused)) static void flush_cpu_icache(void)
 {
-#if defined(CONFIG_CPU_NO_ICACHE)
-  /* No instruction cache */
-#else
+#if defined(CONFIG_CPU_HAS_ICACHE)
   asm volatile(
     ".word(0x100F)\n"
     "nop\n"
@@ -27,9 +25,7 @@ __attribute__((unused)) static void flush_cpu_icache(void)
 
 __attribute__((unused)) static void flush_cpu_dcache(void)
 {
-#if defined(CONFIG_CPU_NO_DCACHE)
-  /* No data cache */
-#else
+#if defined(CONFIG_CPU_HAS_DCACHE)
   asm volatile(".word(0x500F)\n");
 #endif
 }