diff --git a/litex/soc/cores/cpu/vexriscv/core.py b/litex/soc/cores/cpu/vexriscv/core.py
index 1edcc3f7b..db05e1fd4 100644
--- a/litex/soc/cores/cpu/vexriscv/core.py
+++ b/litex/soc/cores/cpu/vexriscv/core.py
@@ -21,6 +21,7 @@ class VexRiscv(Module, AutoCSR):
         self.reset = Signal()
         self.ibus = ibus = wishbone.Interface()
         self.dbus = dbus = wishbone.Interface()
+        self.cpu_reset_address = cpu_reset_address
 
         self.interrupt = Signal(32)
 
@@ -28,7 +29,7 @@ class VexRiscv(Module, AutoCSR):
                 i_clk=ClockSignal(),
                 i_reset=ResetSignal() | self.reset,
 
-                i_externalResetVector=cpu_reset_address,
+                i_externalResetVector=self.cpu_reset_address,
                 i_externalInterruptArray=self.interrupt,
                 i_timerInterrupt=0,