From 739b66a15b2453bb9919a95e6aa926e0e186a5dc Mon Sep 17 00:00:00 2001 From: Charles-Henri Mousset Date: Mon, 15 Apr 2024 09:29:48 +0200 Subject: [PATCH] [fix] Trion T8 have a V1 PLL in BGA packages, but a V2 PLL in TQFP package. DP files varies accordingly --- litex/build/efinix/dbparser.py | 4 ++-- litex/build/efinix/ifacewriter.py | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/litex/build/efinix/dbparser.py b/litex/build/efinix/dbparser.py index 411acc4bf..223fcd2ad 100644 --- a/litex/build/efinix/dbparser.py +++ b/litex/build/efinix/dbparser.py @@ -107,9 +107,9 @@ class EfinixDbParser: peri = root.findall('efxpt:periphery_instance', namespaces) for p in peri: # T20/T120 have instance attribute in single_conn - # not true for T4/T8 -> search in dependency subnode + # not true for T4/T8 (except for TQFP144 package) -> search in dependency subnode if p.get('block') == 'pll': - if self.device[0:2] not in ['T4', 'T8']: + if self.device[0:2] not in ['T4', 'T8'] or self.device[0:6] == "T8Q144": conn = p.findall('efxpt:single_conn', namespaces) for c in conn: i = c.get('instance') diff --git a/litex/build/efinix/ifacewriter.py b/litex/build/efinix/ifacewriter.py index 5ec2a3b88..b3485854a 100644 --- a/litex/build/efinix/ifacewriter.py +++ b/litex/build/efinix/ifacewriter.py @@ -289,7 +289,7 @@ design.create("{2}", "{3}", "./../gateware", overwrite=True) elif block["input_clock"] == "EXTERNAL": # PLL V1 has a different configuration - if partnumber[0:2] in ["T4", "T8"]: + if partnumber[0:2] in ["T4", "T8"] and partnumber != "T8Q144": cmd += 'design.gen_pll_ref_clock("{}", pll_res="{}", refclk_res="{}", refclk_name="{}", ext_refclk_no="{}")\n\n' \ .format(name, block["resource"], block["input_clock_pad"], block["input_clock_name"], block["clock_no"]) else: