From e3e1dcd5477b5dc305fec82645e2850591d0cd2e Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Sun, 5 May 2013 11:53:38 +0200 Subject: [PATCH] dvisampler: add sync polarity detection module (thanks Lars for suggestions) --- milkymist/dvisampler/syncpol.py | 49 +++++++++++++++++++++++++++++++++ 1 file changed, 49 insertions(+) create mode 100644 milkymist/dvisampler/syncpol.py diff --git a/milkymist/dvisampler/syncpol.py b/milkymist/dvisampler/syncpol.py new file mode 100644 index 000000000..2ef752a89 --- /dev/null +++ b/milkymist/dvisampler/syncpol.py @@ -0,0 +1,49 @@ +from migen.fhdl.structure import * +from migen.fhdl.module import Module +from migen.genlib.record import Record + +from milkymist.dvisampler.common import channel_layout + +class SyncPolarity(Module): + def __init__(self): + self.valid_i = Signal() + self.data_in0 = Record(channel_layout) + self.data_in1 = Record(channel_layout) + self.data_in2 = Record(channel_layout) + + self.valid_o = Signal() + self.de = Signal() + self.hsync = Signal() + self.vsync = Signal() + self.r = Signal(8) + self.g = Signal(8) + self.b = Signal(8) + + ### + + de = self.data_in0.de + de_r = Signal() + c = self.data_in0.c + c_polarity = Signal(2) + c_out = Signal(2) + + self.comb += [ + self.de.eq(de_r), + self.hsync.eq(c_out[0]), + self.vsync.eq(c_out[1]) + ] + + self.sync.pix += [ + self.valid_o.eq(self.valid_i), + self.r.eq(self.data_in2.d), + self.g.eq(self.data_in1.d), + self.b.eq(self.data_in0.d), + + de_r.eq(de), + If(de_r & ~de, + c_polarity.eq(c), + c_out.eq(0) + ).Else( + c_out.eq(c ^ c_polarity) + ) + ]