From e44631294a368a839df75c738409b29b1a4fda74 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Thu, 1 Feb 2024 08:34:17 +0100 Subject: [PATCH] CHANGES.md: Update. --- CHANGES.md | 3 +++ 1 file changed, 3 insertions(+) diff --git a/CHANGES.md b/CHANGES.md index 769675550..34b60119c 100644 --- a/CHANGES.md +++ b/CHANGES.md @@ -6,6 +6,7 @@ - interconnect/ahb/AHB2Wishbone : Fixed size check that was too restrictive. - liteeth/phy/gw5rgmii : Fixed Clk assignments. - build/efinix/programmer : Updated for compatibility with latest Efinity versions. + - litespi/software: : Fixed SPI Flash Clk Divider computation when with L2 Cache. [> Added -------- @@ -17,6 +18,8 @@ - cpu/naxriscv : Updated arch definition and added rvc configuration parameters. - cpu/vexriscv_smp : Added csr/clint/plic base address configuration parameters. - liteeth/phy : Added 7-Series/Ultrascale(+) 2500BaseX PHYs. + - litespi/sdrphy: : Allowed flash parameter to be None. + - litespi/integration : Improved integration and simplifications. [> Changed ----------