From 26f5e8a14987db6e2bb8cb53c27de2646234a43b Mon Sep 17 00:00:00 2001 From: Dmitry Derevyanko Date: Fri, 3 May 2024 00:51:01 +0300 Subject: [PATCH] Revert LitexModule for AXILiteSRAM as well. Follows revert d021564fca8ac6d239dad2b18b5531cc9ee249c6 for wishbobe. --- litex/soc/interconnect/axi/axi_lite.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/litex/soc/interconnect/axi/axi_lite.py b/litex/soc/interconnect/axi/axi_lite.py index fb3908daa..6af6d715d 100644 --- a/litex/soc/interconnect/axi/axi_lite.py +++ b/litex/soc/interconnect/axi/axi_lite.py @@ -218,7 +218,7 @@ def axi_lite_to_simple(axi_lite, port_adr, port_dat_r, port_dat_w=None, port_we= # AXI-Lite SRAM ------------------------------------------------------------------------------------ -class AXILiteSRAM(LiteXModule): +class AXILiteSRAM(Module): def __init__(self, mem_or_size, read_only=None, init=None, bus=None, name=None): if bus is None: bus = AXILiteInterface() @@ -257,7 +257,7 @@ class AXILiteSRAM(LiteXModule): port_dat_r = port.dat_r, port_dat_w = port.dat_w if not read_only else None, port_we = port.we if not read_only else None) - self.fsm = fsm + self.submodules.fsm = fsm self.comb += comb # AXI-Lite Data-Width Converter --------------------------------------------------------------------