diff --git a/litex/soc/interconnect/axi/axi_lite.py b/litex/soc/interconnect/axi/axi_lite.py
index 25224c5a5..b5aa754a3 100644
--- a/litex/soc/interconnect/axi/axi_lite.py
+++ b/litex/soc/interconnect/axi/axi_lite.py
@@ -57,6 +57,7 @@ class AXILiteInterface:
         # -----------
         self.data_width    = data_width
         self.address_width = address_width
+        self.bursting      = bursting
         self.addressing    = addressing
         self.clock_domain  = clock_domain