From e4fe0d9ef4dac77ed022574468460a0e42516816 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Wed, 7 Oct 2020 19:32:10 +0200 Subject: [PATCH] soc/cores/spi_flash: fix with_bitbang=False compilation. --- litex/soc/cores/spi_flash.py | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/litex/soc/cores/spi_flash.py b/litex/soc/cores/spi_flash.py index c90f8fc74..d74f2294d 100644 --- a/litex/soc/cores/spi_flash.py +++ b/litex/soc/cores/spi_flash.py @@ -133,8 +133,9 @@ class SpiFlashDualQuad(SpiFlashCommon, AutoCSR): self.specials.dq1 = Tristate(pads.dq[1], o=dq.o[1], i=dq.i[1], oe=dq.oe) if spi_width > 2: # Keep DQ2,DQ3 as outputs during bitbang, this ensures they activate ~WP or ~HOLD functions - self.specials.dq2 = Tristate(pads.dq[2], o=dq.o[2], i=dq.i[2], oe=(dq.oe | self.bitbang_en.storage)) - self.specials.dq3 = Tristate(pads.dq[3], o=dq.o[3], i=dq.i[3], oe=(dq.oe | self.bitbang_en.storage)) + bitbang_en = 0 if not with_bitbang else self.bitbang_en.storage + self.specials.dq2 = Tristate(pads.dq[2], o=dq.o[2], i=dq.i[2], oe=(dq.oe | bitbang_en)) + self.specials.dq3 = Tristate(pads.dq[3], o=dq.o[3], i=dq.i[3], oe=(dq.oe | bitbang_en)) sr = Signal(max(cmd_width, addr_width, wbone_width)) if endianness == "big":