From e50b5d0d45f3f2493eb1a719f75947e803a0e5be Mon Sep 17 00:00:00 2001 From: gatecat Date: Wed, 15 Mar 2023 16:14:09 +0100 Subject: [PATCH] cva6: Fix reset integration Signed-off-by: gatecat --- litex/soc/cores/cpu/cva6/core.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/litex/soc/cores/cpu/cva6/core.py b/litex/soc/cores/cpu/cva6/core.py index caae7600a..ab3bda4e1 100644 --- a/litex/soc/cores/cpu/cva6/core.py +++ b/litex/soc/cores/cpu/cva6/core.py @@ -54,7 +54,7 @@ def add_manifest_sources(platform, manifest): platform.add_verilog_include_path(os.path.join(basedir, res.group(2))) else: filename = res.group(2) - if isinstance(platform, XilinxPlatform): # TODO: other FPGAs + if True: # TODO: other FPGAs if filename.endswith("tc_sram_wrapper.sv"): filename = filename.replace("tc_sram_wrapper.sv", "tc_sram_fpga_wrapper.sv") platform.add_source(os.path.join(basedir, "common/local/techlib/fpga/rtl/SyncSpRamBeNx64.sv")) @@ -119,7 +119,7 @@ class CVA6(CPU): self.cpu_params = dict( # Clk / Rst. i_clk_i = ClockSignal("sys"), - i_rst_n = ~ResetSignal("sys") | self.reset, + i_rst_n = ~ResetSignal("sys") & ~self.reset, # Interrupts i_irq_sources = self.interrupt,