From e53fb88b85447d24868735a2ae344b5bcda5298a Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Fri, 10 Oct 2014 15:33:27 +0800 Subject: [PATCH] uart: minor cleanup and fix --- misoclib/uart/__init__.py | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/misoclib/uart/__init__.py b/misoclib/uart/__init__.py index 126be9d12..f728cd1f0 100644 --- a/misoclib/uart/__init__.py +++ b/misoclib/uart/__init__.py @@ -125,7 +125,7 @@ class UART(Module, AutoCSR): self.tx.sink.stb.eq(0) ), If(self.rx.source.stb, - self._r_rxtx.w.eq(self.rx.source.d) + self._r_rxtx.w.eq(self.rx.source.payload.d) ) ] self.comb += [ @@ -135,9 +135,8 @@ class UART(Module, AutoCSR): class UARTTB(Module): def __init__(self): - MHz=1000000 self.clk_freq = 83333333 - self.baud = 3*MHz + self.baud = 3000000 self.pads = Record([("rx", 1), ("tx", 1)]) self.submodules.slave = UART(self.pads, self.clk_freq, self.baud)