diff --git a/litex/build/vhd2v_converter.py b/litex/build/vhd2v_converter.py
index 05cb1e792..6ff9bd93b 100644
--- a/litex/build/vhd2v_converter.py
+++ b/litex/build/vhd2v_converter.py
@@ -102,8 +102,8 @@ class VHD2VConverter(Module):
         # platform able to synthesis verilog and vhdl -> no conversion
         if self._platform.support_mixed_language and not self._force_convert:
             ip_params = self._params
-            for file in self._files:
-                platform.add_source(file)
+            for file in self._sources:
+                self._platform.add_source(file)
         else: # platform is only able to synthesis verilog -> convert vhdl to verilog
             # check if more than one core is instanciated
             # if so -> append with _X
diff --git a/litex/soc/cores/cpu/microwatt/core.py b/litex/soc/cores/cpu/microwatt/core.py
index f1ed382f2..e65c76e10 100644
--- a/litex/soc/cores/cpu/microwatt/core.py
+++ b/litex/soc/cores/cpu/microwatt/core.py
@@ -172,12 +172,13 @@ class Microwatt(CPU):
 
             # Instruction/Data Cache.
             "cache_ram.vhdl",
-            "plru.vhdl",
+            "plrufn.vhdl",
             "dcache.vhdl",
             "icache.vhdl",
 
             # Decode.
             "insn_helpers.vhdl",
+            "predecode.vhdl",
             "decode1.vhdl",
             "control.vhdl",
             "decode2.vhdl",
@@ -219,8 +220,10 @@ class Microwatt(CPU):
         from litex.build.xilinx import XilinxPlatform
         if isinstance(platform, XilinxPlatform) and not use_ghdl_yosys_plugin:
             sources.append("xilinx-mult.vhdl")
+            sources.append("xilinx-mult-32s.vhdl")
         else:
             sources.append("multiply.vhdl")
+            sources.append("multiply-32s.vhdl")
         sdir = get_data_mod("cpu", "microwatt").data_location
         cdir = os.path.dirname(__file__)
         self.cpu_vhd2v_converter.add_sources(sdir, *sources)
@@ -303,8 +306,7 @@ class XICSSlave(Module, AutoCSR):
         # Add VHDL sources.
         self.add_sources(platform, use_ghdl_yosys_plugin="ghdl" in self.variant)
 
-    @staticmethod
-    def add_sources(platform, use_ghdl_yosys_plugin=False):
+    def add_sources(self, platform, use_ghdl_yosys_plugin=False):
         sources = [
             # Common / Types / Helpers
             "decode_types.vhdl",
@@ -320,8 +322,6 @@ class XICSSlave(Module, AutoCSR):
         cdir = os.path.dirname(__file__)
         self.ics_vhd2v_converter.add_sources(sdir, *sources)
         self.ics_vhd2v_converter.add_source(os.path.join(os.path.dirname(__file__), "xics_wrapper.vhdl"))
-        self.icp_vhd2v_converter.add_sources(sdir, *sources)
-        self.icp_vhd2v_converter.add_source(os.path.join(os.path.dirname(__file__), "xics_wrapper.vhdl"))
 
     def do_finalize(self):
         self.specials += Instance("xics_icp_wrapper", **self.icp_params)
diff --git a/litex_setup.py b/litex_setup.py
index 7972f8b38..f1deedba8 100755
--- a/litex_setup.py
+++ b/litex_setup.py
@@ -112,7 +112,7 @@ git_repos = {
     "pythondata-cpu-marocchino":   GitRepo(url="https://github.com/litex-hub/"),
 
     # OpenPower CPU(s).
-    "pythondata-cpu-microwatt":    GitRepo(url="https://github.com/litex-hub/", sha1=0xb940b55acff),
+    "pythondata-cpu-microwatt":    GitRepo(url="https://github.com/litex-hub/", sha1=0xb4986b23af6),
 
     # RISC-V CPU(s).
     "pythondata-cpu-blackparrot":  GitRepo(url="https://github.com/litex-hub/"),