From f95cf6ab2dff88c67446407dabbf52fb9d6f8be5 Mon Sep 17 00:00:00 2001 From: Joel Stanley Date: Wed, 26 Oct 2022 16:29:53 +1030 Subject: [PATCH 1/3] vhd2v: Fix mixed langauge support Moving to the new vhdl to verilog code broke the Vivado support where there's no conversion required. Signed-off-by: Joel Stanley --- litex/build/vhd2v_converter.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/litex/build/vhd2v_converter.py b/litex/build/vhd2v_converter.py index 05cb1e792..6ff9bd93b 100644 --- a/litex/build/vhd2v_converter.py +++ b/litex/build/vhd2v_converter.py @@ -102,8 +102,8 @@ class VHD2VConverter(Module): # platform able to synthesis verilog and vhdl -> no conversion if self._platform.support_mixed_language and not self._force_convert: ip_params = self._params - for file in self._files: - platform.add_source(file) + for file in self._sources: + self._platform.add_source(file) else: # platform is only able to synthesis verilog -> convert vhdl to verilog # check if more than one core is instanciated # if so -> append with _X From d45d3532fe0cc6c50ec7ec0f5a6531a8cb50dd07 Mon Sep 17 00:00:00 2001 From: Joel Stanley Date: Wed, 26 Oct 2022 16:34:18 +1030 Subject: [PATCH 2/3] microwatt: Update to latest Add the new source files and bump the revision used. Signed-off-by: Joel Stanley --- litex/soc/cores/cpu/microwatt/core.py | 5 ++++- litex_setup.py | 2 +- 2 files changed, 5 insertions(+), 2 deletions(-) diff --git a/litex/soc/cores/cpu/microwatt/core.py b/litex/soc/cores/cpu/microwatt/core.py index f1ed382f2..c613d4783 100644 --- a/litex/soc/cores/cpu/microwatt/core.py +++ b/litex/soc/cores/cpu/microwatt/core.py @@ -172,12 +172,13 @@ class Microwatt(CPU): # Instruction/Data Cache. "cache_ram.vhdl", - "plru.vhdl", + "plrufn.vhdl", "dcache.vhdl", "icache.vhdl", # Decode. "insn_helpers.vhdl", + "predecode.vhdl", "decode1.vhdl", "control.vhdl", "decode2.vhdl", @@ -219,8 +220,10 @@ class Microwatt(CPU): from litex.build.xilinx import XilinxPlatform if isinstance(platform, XilinxPlatform) and not use_ghdl_yosys_plugin: sources.append("xilinx-mult.vhdl") + sources.append("xilinx-mult-32s.vhdl") else: sources.append("multiply.vhdl") + sources.append("multiply-32s.vhdl") sdir = get_data_mod("cpu", "microwatt").data_location cdir = os.path.dirname(__file__) self.cpu_vhd2v_converter.add_sources(sdir, *sources) diff --git a/litex_setup.py b/litex_setup.py index 7972f8b38..f1deedba8 100755 --- a/litex_setup.py +++ b/litex_setup.py @@ -112,7 +112,7 @@ git_repos = { "pythondata-cpu-marocchino": GitRepo(url="https://github.com/litex-hub/"), # OpenPower CPU(s). - "pythondata-cpu-microwatt": GitRepo(url="https://github.com/litex-hub/", sha1=0xb940b55acff), + "pythondata-cpu-microwatt": GitRepo(url="https://github.com/litex-hub/", sha1=0xb4986b23af6), # RISC-V CPU(s). "pythondata-cpu-blackparrot": GitRepo(url="https://github.com/litex-hub/"), From 4ccf9f487d99b4fc23e59fb18b8658c5d936b3c8 Mon Sep 17 00:00:00 2001 From: Joel Stanley Date: Wed, 26 Oct 2022 17:27:15 +1030 Subject: [PATCH 3/3] microwatt: Fix irq variant The vhd2v conversion missed some things that are only run when building the irq variant. Signed-off-by: Joel Stanley --- litex/soc/cores/cpu/microwatt/core.py | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/litex/soc/cores/cpu/microwatt/core.py b/litex/soc/cores/cpu/microwatt/core.py index c613d4783..e65c76e10 100644 --- a/litex/soc/cores/cpu/microwatt/core.py +++ b/litex/soc/cores/cpu/microwatt/core.py @@ -306,8 +306,7 @@ class XICSSlave(Module, AutoCSR): # Add VHDL sources. self.add_sources(platform, use_ghdl_yosys_plugin="ghdl" in self.variant) - @staticmethod - def add_sources(platform, use_ghdl_yosys_plugin=False): + def add_sources(self, platform, use_ghdl_yosys_plugin=False): sources = [ # Common / Types / Helpers "decode_types.vhdl", @@ -323,8 +322,6 @@ class XICSSlave(Module, AutoCSR): cdir = os.path.dirname(__file__) self.ics_vhd2v_converter.add_sources(sdir, *sources) self.ics_vhd2v_converter.add_source(os.path.join(os.path.dirname(__file__), "xics_wrapper.vhdl")) - self.icp_vhd2v_converter.add_sources(sdir, *sources) - self.icp_vhd2v_converter.add_source(os.path.join(os.path.dirname(__file__), "xics_wrapper.vhdl")) def do_finalize(self): self.specials += Instance("xics_icp_wrapper", **self.icp_params)