From e5a7375b307e8384ff92933af345f575ea405d6e Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Thu, 26 Nov 2020 18:54:38 +0100 Subject: [PATCH] cores/clock/ECP5PLL: ensure ECP5PLL's locked is deasserted on reset. It seems EHXPLLL does not loose locked when reseted. --- litex/soc/cores/clock/lattice_ecp5.py | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/litex/soc/cores/clock/lattice_ecp5.py b/litex/soc/cores/clock/lattice_ecp5.py index b143fdbf9..c980916b6 100644 --- a/litex/soc/cores/clock/lattice_ecp5.py +++ b/litex/soc/cores/clock/lattice_ecp5.py @@ -90,6 +90,7 @@ class ECP5PLL(Module): def do_finalize(self): config = self.compute_config() clkfb = Signal() + locked = Signal() self.params.update( attr=[ ("FREQUENCY_PIN_CLKI", str(self.clkin_freq/1e6)), @@ -99,7 +100,7 @@ class ECP5PLL(Module): ("MFG_GMCREF_SEL", "2")], i_RST = self.reset, i_CLKI = self.clkin, - o_LOCK = self.locked, + o_LOCK = locked, p_FEEDBK_PATH = "INT_OS3", # CLKOS3 reserved for feedback with div=1. p_CLKOS3_ENABLE = "ENABLED", p_CLKOS3_DIV = 1, @@ -108,6 +109,7 @@ class ECP5PLL(Module): p_CLKFB_DIV = config["clkfb_div"], p_CLKI_DIV = config["clki_div"], ) + self.comb += self.locked.eq(locked & ~self.reset) for n, (clk, f, p, m) in sorted(self.clkouts.items()): n_to_l = {0: "P", 1: "S", 2: "S2"} div = config["clko{}_div".format(n)]