From e5bf5f42d6188c2c418bd905152137b98d12f314 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Tue, 26 Mar 2013 22:14:25 +0100 Subject: [PATCH] adapt to mibuild & migen changes --- examples/de0_nano/build.py | 15 ++++-------- examples/de0_nano/top.py | 7 ++++-- miscope/bridges/uart2csr/uart.py | 2 +- miscope/miio.py | 10 ++++---- miscope/recorder.py | 39 ++++++++++++++++---------------- miscope/trigger.py | 8 +++---- 6 files changed, 38 insertions(+), 43 deletions(-) diff --git a/examples/de0_nano/build.py b/examples/de0_nano/build.py index 764fe0b2e..9fb0a24d5 100644 --- a/examples/de0_nano/build.py +++ b/examples/de0_nano/build.py @@ -5,25 +5,18 @@ from mibuild.platforms import de0nano import top def main(): - plat = de0nano.Platform() - soc = top.SoC() + platform = de0nano.Platform() + soc = top.SoC(platform) - # set pin constraints - plat.request("led", 0, obj=soc.led) - - #plat.request("led", 4, obj=soc.uart_rx_event.o) - #plat.request("led", 5, obj=soc.uart_tx_event.o) - #plat.request("led", 7, obj=soc.debug_event.o) - plat.request("serial", 0, obj=soc.uart2csr) # set extra constraints - plat.add_platform_command(""" + platform.add_platform_command(""" set_global_assignment -name FAMILY "Cyclone IV E" set_global_assignment -name TOP_LEVEL_ENTITY "top" set_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2005 """) - plat.build_cmdline(soc.get_fragment()) + platform.build_cmdline(soc) if __name__ == "__main__": main() \ No newline at end of file diff --git a/examples/de0_nano/top.py b/examples/de0_nano/top.py index 81592de54..0e3ae09df 100644 --- a/examples/de0_nano/top.py +++ b/examples/de0_nano/top.py @@ -44,7 +44,7 @@ rec_size = 4096 # M I S C O P E E X A M P L E #============================================================================== class SoC(Module): - def __init__(self): + def __init__(self, platform): # MiIo self.submodules.miio = miio.MiIo(MIIO_ADDR, 8, "IO") @@ -57,6 +57,9 @@ class SoC(Module): # Uart2Csr self.submodules.uart2csr = uart2csr.Uart2Csr(clk_freq, 115200) + uart_pads = platform.request("serial") + self.comb += uart_pads.tx.eq(self.uart2csr.tx) + self.comb += self.uart2csr.rx.eq(uart_pads.rx) # Csr Interconnect self.submodules.csrcon = csr.Interconnect(self.uart2csr.csr, @@ -67,7 +70,7 @@ class SoC(Module): ]) # Led - self.led = Signal(8) + self.led = platform.request("user_led", 0, 8) # Misc self.cnt = Signal(9) diff --git a/miscope/bridges/uart2csr/uart.py b/miscope/bridges/uart2csr/uart.py index 12d46c376..fe2e9e060 100644 --- a/miscope/bridges/uart2csr/uart.py +++ b/miscope/bridges/uart2csr/uart.py @@ -65,7 +65,7 @@ class UART(Module): # RX rx = Signal() - self.specials += MultiReg(self.rx, "ext", rx, "sys") + self.specials += MultiReg(self.rx, rx, "sys") rx_r = Signal() rx_reg = Signal(8) rx_bitcount = Signal(4) diff --git a/miscope/miio.py b/miscope/miio.py index d104928a6..43ad3750b 100644 --- a/miscope/miio.py +++ b/miscope/miio.py @@ -16,22 +16,22 @@ class MiIo: if "I" in self.mode: self.i = Signal(self.width) - self.ireg = description.RegisterField("i", self.width, READ_ONLY, WRITE_ONLY) + self._r_i = description.RegisterField(self.width, READ_ONLY, WRITE_ONLY) if "O" in self.mode: self.o = Signal(self.width) - self.oreg = description.RegisterField("o", self.width) + self._r_o = description.RegisterField(self.width) - self.bank = csrgen.Bank([self.oreg, self.ireg], address=self.address) + self.bank = csrgen.Bank([self._r_o, self._r_i], address=self.address) def get_fragment(self): comb = [] if "I" in self.mode: - comb += [self.ireg.field.w.eq(self.i)] + comb += [self._r_i.field.w.eq(self.i)] if "O" in self.mode: - comb += [self.o.eq(self.oreg.field.r)] + comb += [self.o.eq(self._r_o.field.r)] return Fragment(comb) + self.bank.get_fragment() # diff --git a/miscope/recorder.py b/miscope/recorder.py index 2d6346781..7eb0a8a7a 100644 --- a/miscope/recorder.py +++ b/miscope/recorder.py @@ -215,21 +215,20 @@ class Recorder: self.rle = RLE(self.width, (2**(width-2))) # csr interface - self._rst = RegisterField("rst", reset=1) - self._rle = RegisterField("rle", reset=0) - self._arm = RegisterField("arm", reset=0) - self._done = RegisterField("done", reset=0, access_bus=READ_ONLY, + self._r_rst = RegisterField(reset=1) + self._r_rle = RegisterField(reset=0) + self._r_arm = RegisterField(reset=0) + self._r_done = RegisterField(reset=0, access_bus=READ_ONLY, access_dev=WRITE_ONLY) - self._size = RegisterField("size", self.depth_width, reset=1) - self._offset = RegisterField("offset", self.depth_width, reset=1) + self._r_size = RegisterField(self.depth_width, reset=1) + self._r_offset = RegisterField(self.depth_width, reset=1) - self._pull_stb = RegisterField("pull_stb", reset=0) - self._pull_dat = RegisterField("pull_dat", self.width, reset=1, - access_bus=READ_ONLY, access_dev=WRITE_ONLY) + self._r_pull_stb = RegisterField(reset=0) + self._r_pull_dat = RegisterField(self.width, reset=1, access_bus=READ_ONLY, access_dev=WRITE_ONLY) - self.regs = [self._rst, self._rle, self._arm, self._done, self._size, self._offset, - self._pull_stb, self._pull_dat] + self.regs = [self._r_rst, self._r_rle, self._r_arm, self._r_done, self._r_size, self._r_offset, + self._r_pull_stb, self._r_pull_dat] # set address / interface self.set_address(address) @@ -248,22 +247,22 @@ class Recorder: def get_fragment(self): - _pull_stb_rising = RisingEdge(self._pull_stb.field.r) + _pull_stb_rising = RisingEdge(self._r_pull_stb.field.r) # Bank <--> Storage / Sequencer comb = [ - self.sequencer.rst.eq(self._rst.field.r), - self.storage.rst.eq(self._rst.field.r), + self.sequencer.rst.eq(self._r_rst.field.r), + self.storage.rst.eq(self._r_rst.field.r), - self.rle.enable.eq(self._rle.field.r), - self.sequencer.arm.eq(self._arm.field.r), - self.storage.offset.eq(self._offset.field.r), - self.storage.size.eq(self._size.field.r), + self.rle.enable.eq(self._r_rle.field.r), + self.sequencer.arm.eq(self._r_arm.field.r), + self.storage.offset.eq(self._r_offset.field.r), + self.storage.size.eq(self._r_size.field.r), - self._done.field.w.eq(~self.sequencer.enable), + self._r_done.field.w.eq(~self.sequencer.enable), self.storage.pull_stb.eq(_pull_stb_rising.o), - self._pull_dat.field.w.eq(self.storage.pull_dat) + self._r_pull_dat.field.w.eq(self.storage.pull_dat) ] # Storage <--> Sequencer <--> Trigger diff --git a/miscope/trigger.py b/miscope/trigger.py index d0346c18b..04013c2a5 100644 --- a/miscope/trigger.py +++ b/miscope/trigger.py @@ -262,13 +262,13 @@ class Trigger: # generate ports csr registers fields for port in self.ports: - rf = RegisterField(port.reg_p.name, port.reg_p.size, reset=0, - access_bus=WRITE_ONLY, access_dev=READ_ONLY) + rf = RegisterField(port.reg_p.size, reset=0, access_bus=WRITE_ONLY, + access_dev=READ_ONLY, name=port.reg_p.name) setattr(self, port.reg_p.name, rf) # generate sum csr registers fields - self.sum_reg = RegisterField(self.sum.reg_p.name, self.sum.reg_p.size, reset=0, - access_bus=WRITE_ONLY, access_dev=READ_ONLY) + self.sum_reg = RegisterField(self.sum.reg_p.size, reset=0, access_bus=WRITE_ONLY, + access_dev=READ_ONLY, name=self.sum.reg_p.name) # generate registers self.regs = list_regs(self.__dict__)