From ea0427328167638cb0f47944df594abf195e786e Mon Sep 17 00:00:00 2001 From: Gwenhael Goavec-Merou Date: Fri, 12 Nov 2021 11:34:03 +0100 Subject: [PATCH 1/2] soc/cores/cpu/eos_s3: add interrupt support --- litex/soc/cores/cpu/eos_s3/core.py | 3 ++- litex/soc/integration/soc.py | 5 +++++ 2 files changed, 7 insertions(+), 1 deletion(-) diff --git a/litex/soc/cores/cpu/eos_s3/core.py b/litex/soc/cores/cpu/eos_s3/core.py index ef5699fca..3e66770af 100644 --- a/litex/soc/cores/cpu/eos_s3/core.py +++ b/litex/soc/cores/cpu/eos_s3/core.py @@ -36,6 +36,7 @@ class EOS_S3(CPU): def __init__(self, platform, variant): self.platform = platform self.reset = Signal() + self.interrupt = Signal(4) self.periph_buses = [] # Peripheral buses (Connected to main SoC's bus). self.memory_buses = [] # Memory buses (Connected directly to LiteDRAM). @@ -72,7 +73,7 @@ class EOS_S3(CPU): #SDMA_Done(), #SDMA_Active(), # FB Interrupts - #FB_msg_out(4'b0000), + i_FB_msg_out = self.interrupt, #FB_Int_Clr(8'h0), #FB_Start(), #FB_Busy= 0, diff --git a/litex/soc/integration/soc.py b/litex/soc/integration/soc.py index 3687b9251..8c9d6fcb7 100644 --- a/litex/soc/integration/soc.py +++ b/litex/soc/integration/soc.py @@ -926,6 +926,11 @@ class SoC(Module): # Add Bus Masters/CSR/IRQs. if isinstance(self.cpu, cpu.EOS_S3): self.bus.add_master(master=self.cpu.wb) + if hasattr(self.cpu, "interrupt"): + self.irq.enable() + for name, loc in self.cpu.interrupts.items(): + self.irq.add(name, loc) + self.add_config("CPU_HAS_INTERRUPT") if not isinstance(self.cpu, (cpu.CPUNone, cpu.Zynq7000, cpu.EOS_S3)): if reset_address is None: reset_address = self.mem_map["rom"] From b703980c86f16235504dff4b4e43510ab8e09be3 Mon Sep 17 00:00:00 2001 From: Gwenhael Goavec-Merou Date: Sat, 13 Nov 2021 18:33:29 +0100 Subject: [PATCH 2/2] soc/cores/cpu/eos_s3: fix o_WBs_ADR align --- litex/soc/cores/cpu/eos_s3/core.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/litex/soc/cores/cpu/eos_s3/core.py b/litex/soc/cores/cpu/eos_s3/core.py index 3e66770af..f00efd068 100644 --- a/litex/soc/cores/cpu/eos_s3/core.py +++ b/litex/soc/cores/cpu/eos_s3/core.py @@ -43,7 +43,7 @@ class EOS_S3(CPU): self.wishbone_master = [] # General Purpose Wishbone Masters. # # # - self.wb = wishbone.Interface(data_width=32, adr_width=17) + self.wb = wishbone.Interface(data_width=32, adr_width=15) # EOS-S3 Clocking. self.clock_domains.cd_Sys_Clk0 = ClockDomain() @@ -58,7 +58,7 @@ class EOS_S3(CPU): # AHB-To-FPGA Bridge i_WB_CLK = ClockSignal("Sys_Clk0"), o_WB_RST = WB_RST, - o_WBs_ADR = self.wb.adr, + o_WBs_ADR = Cat(Signal(2), self.wb.adr), o_WBs_CYC = self.wb.cyc, o_WBs_BYTE_STB = self.wb.sel, o_WBs_WE = self.wb.we,