From e6171e79dbeff9922220c5becc9dbb953ff736ce Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Tue, 9 Jul 2024 10:00:21 +0200 Subject: [PATCH] build/efinix: Fix typos (thanks @AndrewD). --- litex/build/efinix/efinity.py | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/litex/build/efinix/efinity.py b/litex/build/efinix/efinity.py index 5322536b3..eeb85e983 100644 --- a/litex/build/efinix/efinity.py +++ b/litex/build/efinix/efinity.py @@ -317,12 +317,12 @@ class EfinityToolchain(GenericToolchain): "--infer-clk-enable", self._infer_clk_enable, "--infer-sync-set-reset", "1", "--fanout-limit", "0", - "--bram_output_regs_packing", self._bram_output_regs_packaging, + "--bram_output_regs_packing", self._bram_output_regs_packing, "--retiming", self._retiming, "--seq_opt", self._seq_opt, "--blast_const_operand_adders", "1", - "--mult_input_regs_packing", self._mult_input_regs_packaging, - "--mult_output_regs_packing", self._mult_output_regs_packaing, + "--mult_input_regs_packing", self._mult_input_regs_packing, + "--mult_output_regs_packing", self._mult_output_regs_packing, "--veri_option", "verilog_mode=verilog_2k,vhdl_mode=vhdl_2008", "--work-dir", "work_syn", "--output-dir", "outflow", @@ -412,6 +412,7 @@ def build_args(parser): choices=["0", "1"]), toolchain.add_argument("--mult-output-regs-packing", default="1", help="Allow packing of multiplier output registers.", choices=["0", "1"]) + def build_argdict(args): return { "synth_mode" : args.synth_mode,