From e6681bbb9c647157905585b7889b4339f5545634 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Mon, 25 Apr 2016 19:14:20 +0200 Subject: [PATCH] soc/interconnect/wishbone: add FlipFlop (should be removed) --- litex/soc/interconnect/wishbone.py | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/litex/soc/interconnect/wishbone.py b/litex/soc/interconnect/wishbone.py index 48d002c40..73ba6e0ba 100644 --- a/litex/soc/interconnect/wishbone.py +++ b/litex/soc/interconnect/wishbone.py @@ -10,6 +10,13 @@ from litex.gen.genlib.fsm import FSM, NextState from litex.soc.interconnect import csr # TODO: rewrite without FlipFlop and Counter +@ResetInserter() +@CEInserter() +class FlipFlop(Module): + def __init__(self, *args, **kwargs): + self.d = Signal(*args, **kwargs) + self.q = Signal(*args, **kwargs) + self.sync += self.q.eq(self.d) _layout = [