diff --git a/litex/soc/cores/cpu/minerva/core.py b/litex/soc/cores/cpu/minerva/core.py
index 731945463..05007cf51 100644
--- a/litex/soc/cores/cpu/minerva/core.py
+++ b/litex/soc/cores/cpu/minerva/core.py
@@ -22,7 +22,7 @@ class Minerva(Module):
 
     @property
     def gcc_triple(self):
-        return ("riscv64-unknown-elf", "riscv32-unknown-elf")
+        return ("riscv64-unknown-elf", "riscv32-unknown-elf", "riscv-none-embed")
 
     @property
     def gcc_flags(self):
diff --git a/litex/soc/cores/cpu/picorv32/core.py b/litex/soc/cores/cpu/picorv32/core.py
index 40b9c5b64..7a3c5600e 100644
--- a/litex/soc/cores/cpu/picorv32/core.py
+++ b/litex/soc/cores/cpu/picorv32/core.py
@@ -40,7 +40,7 @@ class PicoRV32(Module):
 
     @property
     def gcc_triple(self):
-        return ("riscv64-unknown-elf", "riscv32-unknown-elf")
+        return ("riscv64-unknown-elf", "riscv32-unknown-elf", "riscv-none-embed")
 
     @property
     def gcc_flags(self):
diff --git a/litex/soc/cores/cpu/vexriscv/core.py b/litex/soc/cores/cpu/vexriscv/core.py
index 2111375ba..6c6cc08b4 100644
--- a/litex/soc/cores/cpu/vexriscv/core.py
+++ b/litex/soc/cores/cpu/vexriscv/core.py
@@ -84,7 +84,7 @@ class VexRiscv(Module, AutoCSR):
 
     @property
     def gcc_triple(self):
-        return ("riscv64-unknown-elf", "riscv32-unknown-elf")
+        return ("riscv64-unknown-elf", "riscv32-unknown-elf", "riscv-none-embed")
 
     @property
     def gcc_flags(self):