From e6e3a909f297ac6ce833600df5acb3197a58a545 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Thu, 17 Mar 2022 16:00:05 +0100 Subject: [PATCH] cpu/vexriscv_smp: Set UART/Timer0 CSRs as done on NaxRiscv to ensure OpenSBI compatibility. This also allow generating bitstreams for Linux-on-LiteX-VexRiscv directly from litex-boards. --- litex/soc/cores/cpu/naxriscv/core.py | 1 + litex/soc/cores/cpu/vexriscv_smp/core.py | 4 ++++ 2 files changed, 5 insertions(+) diff --git a/litex/soc/cores/cpu/naxriscv/core.py b/litex/soc/cores/cpu/naxriscv/core.py index e7991495f..e97c79622 100644 --- a/litex/soc/cores/cpu/naxriscv/core.py +++ b/litex/soc/cores/cpu/naxriscv/core.py @@ -254,6 +254,7 @@ class NaxRiscv(CPU): platform.add_source(os.path.join(vdir, self.netlist_name + ".v"), "verilog") def add_soc_components(self, soc, soc_region_cls): + # Set UART/Timer0 CSRs to the ones used by OpenSBI. soc.csr.add("uart", n=2) soc.csr.add("timer0", n=3) diff --git a/litex/soc/cores/cpu/vexriscv_smp/core.py b/litex/soc/cores/cpu/vexriscv_smp/core.py index 4a8b9d105..c198e0f25 100755 --- a/litex/soc/cores/cpu/vexriscv_smp/core.py +++ b/litex/soc/cores/cpu/vexriscv_smp/core.py @@ -375,6 +375,10 @@ class VexRiscvSMP(CPU): platform.add_source(os.path.join(vdir, self.cluster_name + ".v"), "verilog") def add_soc_components(self, soc, soc_region_cls): + # Set UART/Timer0 CSRs to the ones used by OpenSBI. + soc.csr.add("uart", n=2) + soc.csr.add("timer0", n=3) + # Define number of CPUs soc.add_config("CPU_COUNT", VexRiscvSMP.cpu_count) soc.add_constant("CPU_ISA", VexRiscvSMP.get_arch())