From e6f1d677e7bd04088fc51e2515857c25f96e9239 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Wed, 3 Mar 2021 08:59:51 +0100 Subject: [PATCH] soc/cores/freqmeter: Minor cosmetic cleanups. --- litex/soc/cores/freqmeter.py | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/litex/soc/cores/freqmeter.py b/litex/soc/cores/freqmeter.py index 0ed5cfda6..b7794ee51 100644 --- a/litex/soc/cores/freqmeter.py +++ b/litex/soc/cores/freqmeter.py @@ -15,26 +15,26 @@ from litex.soc.interconnect.csr import * class _Sampler(Module): def __init__(self, width): self.latch = Signal() - self.i = Signal(width) - self.o = Signal(32) + self.i = Signal(width) + self.o = Signal(32) # # # - inc = Signal(width) - counter = Signal(32) + inc = Signal(width) + count = Signal(32) # Use wrapping property of unsigned arithmeric to reset the counter at each cycle. Doing - # it in fmeter clock domain would not be reliable. + # it in FreqMeter clock domain would not be reliable. i_d = Signal(width) self.sync += i_d.eq(self.i) self.comb += inc.eq(self.i - i_d) - self.sync += \ + self.sync += [ + count.eq(count + inc), If(self.latch, - counter.eq(0), - self.o.eq(counter), - ).Else( - counter.eq(counter + inc) + count.eq(0), + self.o.eq(count) ) + ] # Freq Meter ---------------------------------------------------------------------------------------