From e6f97e08d26b217d155c5df0dd1430eaf1d92651 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Mon, 4 Mar 2019 09:27:31 +0100 Subject: [PATCH] targets/ulx3s: use AsyncResetSynchronizer and derivate sys_clk/sys_clk_ps constraints from clk25 Now supported by Trellis/Nextpnr. --- litex/boards/targets/ulx3s.py | 7 ++----- 1 file changed, 2 insertions(+), 5 deletions(-) diff --git a/litex/boards/targets/ulx3s.py b/litex/boards/targets/ulx3s.py index 4a2ecf296..28da467fb 100755 --- a/litex/boards/targets/ulx3s.py +++ b/litex/boards/targets/ulx3s.py @@ -26,6 +26,7 @@ class _CRG(Module): # clk / rst clk25 = platform.request("clk25") rst = platform.request("rst") + platform.add_period_constraint(clk25, 40.0) # pll self.submodules.pll = pll = ECP5PLL() @@ -33,11 +34,7 @@ class _CRG(Module): pll.register_clkin(clk25, 25e6) pll.create_clkout(self.cd_sys, 50e6, phase=11) pll.create_clkout(self.cd_sys_ps, 50e6, phase=20) - # FIXME: AsyncResetSynchronizer needs FD1S3BX support. - #self.specials += AsyncResetSynchronizer(self.cd_sys, rst) - self.comb += self.cd_sys.rst.eq(rst) - platform.add_period_constraint(self.cd_sys.clk, 20.0) - platform.add_period_constraint(self.cd_sys_ps.clk, 20.0) + self.specials += AsyncResetSynchronizer(self.cd_sys, rst) # sdram clock self.comb += platform.request("sdram_clock").eq(self.cd_sys_ps.clk)