From f8c58216580e223558b539fa3f9a0a6969bdf9a3 Mon Sep 17 00:00:00 2001
From: Arnaud Durand <arnaud.durand@unifr.ch>
Date: Thu, 19 Dec 2019 08:53:44 +0100
Subject: [PATCH 1/2] Revert "gen/fhdl/verilog: allow single element verilog
 inline attribute"

This reverts commit b845755995a8517d8e0ffa86156fb5577201f7d4.
---
 litex/build/lattice/diamond.py |  2 ++
 litex/gen/fhdl/verilog.py      | 17 +++++++++--------
 2 files changed, 11 insertions(+), 8 deletions(-)

diff --git a/litex/build/lattice/diamond.py b/litex/build/lattice/diamond.py
index dc3c5146c..3e192d930 100644
--- a/litex/build/lattice/diamond.py
+++ b/litex/build/lattice/diamond.py
@@ -10,6 +10,8 @@ import shutil
 
 from migen.fhdl.structure import _Fragment
 
+from litex.gen.fhdl.verilog import DummyAttrTranslate
+
 from litex.build.generic_platform import *
 from litex.build import tools
 from litex.build.lattice import common
diff --git a/litex/gen/fhdl/verilog.py b/litex/gen/fhdl/verilog.py
index b0fc69fac..0e34af26f 100644
--- a/litex/gen/fhdl/verilog.py
+++ b/litex/gen/fhdl/verilog.py
@@ -198,13 +198,11 @@ def _printattr(attr, attr_translate):
     firsta = True
     for attr in sorted(attr,
                        key=lambda x: ("", x) if isinstance(x, str) else x):
-        # platform-dependent attribute
         if isinstance(attr, tuple):
+            # platform-dependent attribute
             attr_name, attr_value = attr
-        elif attr not in attr_translate.keys():
-            attr_name, attr_value = attr, None
-        # translated attribute
         else:
+            # translated attribute
             at = attr_translate[attr]
             if at is None:
                 continue
@@ -212,9 +210,7 @@ def _printattr(attr, attr_translate):
         if not firsta:
             r += ", "
         firsta = False
-        r += attr_name
-        if attr_value is not None:
-            r += " = \"" + attr_value + "\""
+        r += attr_name + " = \"" + attr_value + "\""
     if r:
         r = "(* " + r + " *)"
     return r
@@ -370,9 +366,14 @@ def _printspecials(overrides, specials, ns, add_data_file, attr_translate):
     return r
 
 
+class DummyAttrTranslate:
+    def __getitem__(self, k):
+        return (k, "true")
+
+
 def convert(f, ios=None, name="top",
   special_overrides=dict(),
-  attr_translate={},
+  attr_translate=DummyAttrTranslate(),
   create_clock_domains=True,
   display_run=False,
   reg_initialization=True,

From 94e239ff13325a332dd5a3932ff08bc0426b5d44 Mon Sep 17 00:00:00 2001
From: Arnaud Durand <arnaud.durand@unifr.ch>
Date: Thu, 19 Dec 2019 09:03:12 +0100
Subject: [PATCH 2/2] Add integer attributes

---
 litex/gen/fhdl/verilog.py | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/litex/gen/fhdl/verilog.py b/litex/gen/fhdl/verilog.py
index 0e34af26f..e1bd8da4e 100644
--- a/litex/gen/fhdl/verilog.py
+++ b/litex/gen/fhdl/verilog.py
@@ -210,7 +210,8 @@ def _printattr(attr, attr_translate):
         if not firsta:
             r += ", "
         firsta = False
-        r += attr_name + " = \"" + attr_value + "\""
+        const_expr = "\"" + attr_value + "\"" if not isinstance(attr_value, int) else str(attr_value)
+        r += attr_name + " = " + const_expr
     if r:
         r = "(* " + r + " *)"
     return r