From e8262ed44792eb46fb1164e62446f289a9613159 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Wed, 2 Dec 2015 14:18:09 +0100 Subject: [PATCH] build: pass build_name to get_verilog (same name for top module and top level file) --- litex/build/altera/quartus.py | 4 ++-- litex/build/lattice/diamond.py | 4 ++-- litex/build/xilinx/ise.py | 4 ++-- litex/build/xilinx/vivado.py | 4 ++-- 4 files changed, 8 insertions(+), 8 deletions(-) diff --git a/litex/build/altera/quartus.py b/litex/build/altera/quartus.py index cdab36be3..e7a27622d 100644 --- a/litex/build/altera/quartus.py +++ b/litex/build/altera/quartus.py @@ -113,7 +113,7 @@ quartus_sta {build_name} -c {build_name} class AlteraQuartusToolchain: def build(self, platform, fragment, build_dir="build", build_name="top", - toolchain_path="/opt/Altera", run=True): + toolchain_path="/opt/Altera", run=True, **kwargs): cwd = os.getcwd() tools.mkdir_noerror(build_dir) os.chdir(build_dir) @@ -122,7 +122,7 @@ class AlteraQuartusToolchain: fragment = fragment.get_fragment() platform.finalize(fragment) - v_output = platform.get_verilog(fragment) + v_output = platform.get_verilog(fragment, name=build_name, **kwargs) named_sc, named_pc = platform.resolve_signals(v_output.ns) v_file = build_name + ".v" v_output.write(v_file) diff --git a/litex/build/lattice/diamond.py b/litex/build/lattice/diamond.py index 857fef021..68d1db449 100644 --- a/litex/build/lattice/diamond.py +++ b/litex/build/lattice/diamond.py @@ -76,7 +76,7 @@ def _run_diamond(build_name, source, ver=None): class LatticeDiamondToolchain: def build(self, platform, fragment, build_dir="build", build_name="top", - toolchain_path="/opt/Diamond", run=True): + toolchain_path="/opt/Diamond", run=True, **kwargs): tools.mkdir_noerror(build_dir) cwd = os.getcwd() os.chdir(build_dir) @@ -85,7 +85,7 @@ class LatticeDiamondToolchain: fragment = fragment.get_fragment() platform.finalize(fragment) - v_output = platform.get_verilog(fragment) + v_output = platform.get_verilog(fragment, name=build_name, **kwargs) named_sc, named_pc = platform.resolve_signals(v_output.ns) v_file = build_name + ".v" v_output.write(v_file) diff --git a/litex/build/xilinx/ise.py b/litex/build/xilinx/ise.py index e2d29ac39..374bffc08 100644 --- a/litex/build/xilinx/ise.py +++ b/litex/build/xilinx/ise.py @@ -133,7 +133,7 @@ class XilinxISEToolchain: self.ise_commands = "" def build(self, platform, fragment, build_dir="build", build_name="top", - toolchain_path=None, source=None, run=True, mode="xst"): + toolchain_path=None, source=None, run=True, mode="xst", **kwargs): if not isinstance(fragment, _Fragment): fragment = fragment.get_fragment() if toolchain_path is None: @@ -155,7 +155,7 @@ class XilinxISEToolchain: os.chdir(build_dir) try: if mode == "xst" or mode == "yosys": - v_output = platform.get_verilog(fragment) + v_output = platform.get_verilog(fragment, name=build_name, **kwargs) vns = v_output.ns named_sc, named_pc = platform.resolve_signals(vns) v_file = build_name + ".v" diff --git a/litex/build/xilinx/vivado.py b/litex/build/xilinx/vivado.py index 557016e72..032b78bbe 100644 --- a/litex/build/xilinx/vivado.py +++ b/litex/build/xilinx/vivado.py @@ -112,7 +112,7 @@ class XilinxVivadoToolchain: tools.write_to_file(build_name + ".tcl", "\n".join(tcl)) def build(self, platform, fragment, build_dir="build", build_name="top", - toolchain_path="/opt/Xilinx/Vivado", source=True, run=True): + toolchain_path="/opt/Xilinx/Vivado", source=True, run=True, **kwargs): tools.mkdir_noerror(build_dir) cwd = os.getcwd() os.chdir(build_dir) @@ -120,7 +120,7 @@ class XilinxVivadoToolchain: if not isinstance(fragment, _Fragment): fragment = fragment.get_fragment() platform.finalize(fragment) - v_output = platform.get_verilog(fragment) + v_output = platform.get_verilog(fragment, name=build_name, **kwargs) named_sc, named_pc = platform.resolve_signals(v_output.ns) v_file = build_name + ".v" v_output.write(v_file)