From 5307b5e3f20f6161da4f18b556facd47e18e641c Mon Sep 17 00:00:00 2001 From: stone3311 Date: Fri, 23 Dec 2022 16:51:35 +0100 Subject: [PATCH] build/altera: Fix IP integration --- litex/build/altera/quartus.py | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/litex/build/altera/quartus.py b/litex/build/altera/quartus.py index 1f6d5a8ff..61877283e 100644 --- a/litex/build/altera/quartus.py +++ b/litex/build/altera/quartus.py @@ -138,10 +138,9 @@ class AlteraQuartusToolchain(GenericToolchain): if fpath not in platform.verilog_include_paths: platform.verilog_include_paths.append(fpath) - # Add ips + # Add IPs for filename in self.platform.ips: - tpl = "set_global_assignment -name QSYS_FILE {filename}" - qsf.append(tpl.replace(filename=filename.replace("\\", "/"))) + qsf.append("set_global_assignment -name QSYS_FILE " + filename.replace("\\", "/")) # Add include paths for path in self.platform.verilog_include_paths: