diff --git a/litex/tools/litex_server.py b/litex/tools/litex_server.py
index 01d0401ae..098363230 100755
--- a/litex/tools/litex_server.py
+++ b/litex/tools/litex_server.py
@@ -165,6 +165,8 @@ def main():
                         help="Host bind address")
     parser.add_argument("--bind-port", default=1234,
                         help="Host bind port")
+    parser.add_argument("--debug", action="store_true",
+                        help="Turn on debug for comm")
 
     # UART arguments
     parser.add_argument("--uart", action="store_true",
@@ -208,13 +210,13 @@ def main():
         uart_port = args.uart_port
         uart_baudrate = int(float(args.uart_baudrate))
         print("[CommUART] port: {} / baudrate: {} / ".format(uart_port, uart_baudrate), end="")
-        comm = CommUART(uart_port, uart_baudrate)
+        comm = CommUART(uart_port, uart_baudrate, args.debug)
     elif args.udp:
         from litex.tools.remote.comm_udp import CommUDP
         udp_ip = args.udp_ip
         udp_port = int(args.udp_port)
         print("[CommUDP] ip: {} / port: {} / ".format(udp_ip, udp_port), end="")
-        comm = CommUDP(udp_ip, udp_port)
+        comm = CommUDP(udp_ip, udp_port, args.debug)
     elif args.pcie:
         from litex.tools.remote.comm_pcie import CommPCIe
         pcie_bar = args.pcie_bar
@@ -230,7 +232,7 @@ def main():
             enable.write("1")
         enable.close()
         print("[CommPCIe] bar: {} / ".format(pcie_bar), end="")
-        comm = CommPCIe(pcie_bar)
+        comm = CommPCIe(pcie_bar, args.debug)
     elif args.usb:
         from litex.tools.remote.comm_usb import CommUSB
         if args.usb_pid is None and args.usb_vid is None:
@@ -243,7 +245,7 @@ def main():
         vid = args.usb_vid
         if vid is not None:
             vid = int(vid, base=0)
-        comm = CommUSB(vid=vid, pid=pid, max_retries=args.usb_max_retries)
+        comm = CommUSB(vid=vid, pid=pid, max_retries=args.usb_max_retries, debug=args.debug)
     else:
         parser.print_help()
         exit()
diff --git a/litex/tools/litex_sim.py b/litex/tools/litex_sim.py
index 5ad3b030d..5eeca9004 100755
--- a/litex/tools/litex_sim.py
+++ b/litex/tools/litex_sim.py
@@ -316,7 +316,7 @@ class SimSoC(SoCCore):
         if with_sdcard:
             self.add_sdcard("sdcard", use_emulator=True)
 
-        # Simulatio debugging ----------------------------------------------------------------------
+        # Simulation debugging ----------------------------------------------------------------------
         if sim_debug:
             platform.add_debug(self, reset=1 if trace_reset_on else 0)
         else:
@@ -324,8 +324,7 @@ class SimSoC(SoCCore):
 
 # Build --------------------------------------------------------------------------------------------
 
-def main():
-    parser = argparse.ArgumentParser(description="Generic LiteX SoC Simulation")
+def add_sim_args(parser):
     builder_args(parser)
     soc_sdram_args(parser)
     parser.add_argument("--threads",              default=1,               help="Set number of threads (default=1)")
@@ -350,6 +349,13 @@ def main():
     parser.add_argument("--trace-end",            default="-1",            help="Time to end tracing (ps)")
     parser.add_argument("--opt-level",            default="O3",            help="Compilation optimization level")
     parser.add_argument("--sim-debug",            action="store_true",     help="Add simulation debugging modules")
+
+# Build --------------------------------------------------------------------------------------------
+
+def main():
+    parser = argparse.ArgumentParser(description="Generic LiteX SoC Simulation")
+    add_sim_args(parser)
+
     args = parser.parse_args()
 
     soc_kwargs     = soc_sdram_argdict(args)