From e8ed29776345a119c9a2e094915ba04793c9590b Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Mon, 28 Mar 2022 16:03:14 +0200 Subject: [PATCH] cpu/vexriscv_smp: Fix pbus width when using direct LiteDRAM interface (always 32-bit). --- litex/soc/cores/cpu/vexriscv_smp/core.py | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/litex/soc/cores/cpu/vexriscv_smp/core.py b/litex/soc/cores/cpu/vexriscv_smp/core.py index 8ebd4c09a..524f7dbce 100755 --- a/litex/soc/cores/cpu/vexriscv_smp/core.py +++ b/litex/soc/cores/cpu/vexriscv_smp/core.py @@ -282,8 +282,12 @@ class VexRiscvSMP(CPU): self.jtag_tdo = Signal() self.jtag_tdi = Signal() self.interrupt = Signal(32) - self.pbus = pbus = wishbone.Interface(data_width=max(VexRiscvSMP.icache_width, VexRiscvSMP.dcache_width)) - + self.pbus = pbus = wishbone.Interface(data_width={ + # Always 32-bit when using direct LiteDRAM interfaces. + False : 32, + # Else max of I/DCache-width. + True : max(VexRiscvSMP.icache_width, VexRiscvSMP.dcache_width), + }[VexRiscvSMP.wishbone_memory]) self.periph_buses = [pbus] # Peripheral buses (Connected to main SoC's bus). self.memory_buses = [] # Memory buses (Connected directly to LiteDRAM).