From e903b62af1f9b66d3b1f70211e88e7ecd84e6c74 Mon Sep 17 00:00:00 2001
From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Mon, 16 Mar 2015 20:44:29 +0100
Subject: [PATCH] mibuild/altera: use new Toolchain/Platform architecture

---
 mibuild/altera/__init__.py   |  2 ++
 mibuild/altera/common.py     |  1 +
 mibuild/altera/platform.py   | 25 +++++++++++++++++++++++++
 mibuild/altera/quartus.py    | 23 ++++++++++++-----------
 mibuild/platforms/de0nano.py |  6 +++---
 5 files changed, 43 insertions(+), 14 deletions(-)
 create mode 100644 mibuild/altera/common.py
 create mode 100644 mibuild/altera/platform.py

diff --git a/mibuild/altera/__init__.py b/mibuild/altera/__init__.py
index e69de29bb..9a0845803 100644
--- a/mibuild/altera/__init__.py
+++ b/mibuild/altera/__init__.py
@@ -0,0 +1,2 @@
+from mibuild.altera.platform import AlteraPlatform
+from mibuild.altera.programmer import USBBlaster
diff --git a/mibuild/altera/common.py b/mibuild/altera/common.py
new file mode 100644
index 000000000..3303e1807
--- /dev/null
+++ b/mibuild/altera/common.py
@@ -0,0 +1 @@
+altera_special_overrides = {}
diff --git a/mibuild/altera/platform.py b/mibuild/altera/platform.py
new file mode 100644
index 000000000..c98f987fc
--- /dev/null
+++ b/mibuild/altera/platform.py
@@ -0,0 +1,25 @@
+from mibuild.generic_platform import GenericPlatform
+from mibuild.altera import common, quartus
+
+class AlteraPlatform(GenericPlatform):
+	bitstream_ext = ".sof"
+
+	def __init__(self, *args, toolchain="quartus", **kwargs):
+		GenericPlatform.__init__(self, *args, **kwargs)
+		if toolchain == "quartus":
+			self.toolchain = quartus.AlteraQuartusToolchain()
+		else:
+			raise ValueError("Unknown toolchain")
+
+	def get_verilog(self, *args, special_overrides=dict(), **kwargs):
+		so = dict(common.altera_special_overrides)
+		so.update(special_overrides)
+		return GenericPlatform.get_verilog(self, *args, special_overrides=so, **kwargs)
+
+	def build(self, *args, **kwargs):
+		return self.toolchain.build(self, *args, **kwargs)
+
+	def add_period_constraint(self, clk, period):
+		if hasattr(clk, "p"):
+			clk = clk.p
+		self.toolchain.add_period_constraint(self, clk, period)
diff --git a/mibuild/altera/quartus.py b/mibuild/altera/quartus.py
index b5468af0e..49e7d77e7 100644
--- a/mibuild/altera/quartus.py
+++ b/mibuild/altera/quartus.py
@@ -5,7 +5,9 @@ import os, subprocess
 
 from migen.fhdl.structure import _Fragment
 from mibuild.generic_platform import *
+
 from mibuild import tools
+from mibuild.xilinx import common
 
 def _format_constraint(c):
 	if isinstance(c, Pins):
@@ -69,23 +71,22 @@ quartus_sta {build_name} -c {build_name}
 	if r != 0:
 		raise OSError("Subprocess failed")
 
-class AlteraQuartusPlatform(GenericPlatform):
-	bitstream_ext = ".sof"
-	def build(self, fragment, build_dir="build", build_name="top",
+class AlteraQuartusToolchain:
+	def build(self, platform, fragment, build_dir="build", build_name="top",
 			quartus_path="/opt/Altera", run=True):
 		tools.mkdir_noerror(build_dir)
 		os.chdir(build_dir)
 
 		if not isinstance(fragment, _Fragment):
 			fragment = fragment.get_fragment()
-		self.finalize(fragment)
+		platform.finalize(fragment)
 
-		v_src, vns = self.get_verilog(fragment)
-		named_sc, named_pc = self.resolve_signals(vns)
+		v_src, vns = platform.get_verilog(fragment)
+		named_sc, named_pc = platform.resolve_signals(vns)
 		v_file = build_name + ".v"
 		tools.write_to_file(v_file, v_src)
-		sources = self.sources + [(v_file, "verilog")]
-		_build_files(self.device, sources, self.verilog_include_paths, named_sc, named_pc, build_name)
+		sources = platform.sources + [(v_file, "verilog")]
+		_build_files(platform.device, sources, platform.verilog_include_paths, named_sc, named_pc, build_name)
 		if run:
 			_run_quartus(build_name, quartus_path)
 
@@ -93,7 +94,7 @@ class AlteraQuartusPlatform(GenericPlatform):
 
 		return vns
 
-	def add_period_constraint(self, clk, period):
+	def add_period_constraint(self, platform, clk, period):
 		# TODO: handle differential clk
-		self.add_platform_command("""set_global_assignment -name DUTY_CYCLE 50 -section_id {clk}""", clk=clk)
-		self.add_platform_command("""set_global_assignment -name FMAX_REQUIREMENT "{freq} MHz" -section_id {clk}\n""".format(freq=str(float(1/period)*1000), clk="{clk}"), clk=clk)
+		platform.add_platform_command("""set_global_assignment -name DUTY_CYCLE 50 -section_id {clk}""", clk=clk)
+		platform.add_platform_command("""set_global_assignment -name FMAX_REQUIREMENT "{freq} MHz" -section_id {clk}\n""".format(freq=str(float(1/period)*1000), clk="{clk}"), clk=clk)
diff --git a/mibuild/platforms/de0nano.py b/mibuild/platforms/de0nano.py
index 0e0fe3263..c04987ea4 100644
--- a/mibuild/platforms/de0nano.py
+++ b/mibuild/platforms/de0nano.py
@@ -2,7 +2,7 @@
 # License: BSD
 
 from mibuild.generic_platform import *
-from mibuild.altera.quartus import AlteraQuartusPlatform
+from mibuild.altera import AlteraPlatform
 from mibuild.altera.programmer import USBBlaster
 
 _io = [
@@ -90,12 +90,12 @@ _io = [
 	),
 ]
 
-class Platform(AlteraQuartusPlatform):
+class Platform(AlteraPlatform):
 	default_clk_name = "clk50"
 	default_clk_period = 20
 
 	def __init__(self):
-		AlteraQuartusPlatform.__init__(self, "EP4CE22F17C6", _io)
+		AlteraPlatform.__init__(self, "EP4CE22F17C6", _io)
 
 	def create_programmer(self):
 		return USBBlaster()