From e946f6e4538277308e374cd1f0b1b9a31f66dc5a Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Mon, 16 Mar 2015 23:39:32 +0100 Subject: [PATCH] fhdl/verilog: do not use initial begin in _printinit (not accepted by all synthesis tools ex: Synplify Pro does not accept it) --- migen/fhdl/verilog.py | 14 +++++++++++--- 1 file changed, 11 insertions(+), 3 deletions(-) diff --git a/migen/fhdl/verilog.py b/migen/fhdl/verilog.py index b4bd534e9..3b5e4cf5d 100644 --- a/migen/fhdl/verilog.py +++ b/migen/fhdl/verilog.py @@ -276,11 +276,19 @@ def _printinit(f, ios, ns): - ios \ - list_targets(f) \ - list_special_ios(f, False, True, True) + wires = (_list_comb_wires(f) | list_special_ios(f, True, False, False)) \ + - ios \ + - list_targets(f) \ + - list_special_ios(f, False, True, True) if signals: - r += "initial begin\n" for s in sorted(signals, key=lambda x: x.huid): - r += "\t" + ns.get_name(s) + " <= " + _printexpr(ns, s.reset)[0] + ";\n" - r += "end\n\n" + if s in wires: + r += "assign" + ns.get_name(s) + " = " + _printexpr(ns, s.reset)[0] + ";\n" + r += "always @(*) begin\n" + for s in sorted(signals, key=lambda x: x.huid): + if s not in wires: + r += "\t" + ns.get_name(s) + " <= " + _printexpr(ns, s.reset)[0] + ";\n" + r += "end\n" return r def convert(f, ios=None, name="top",