From e9739b5446256f700803c030459a7b1134a35b0c Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Thu, 6 Jul 2023 22:05:23 +0200 Subject: [PATCH] soc: Switch to litex.gen.genlib.misc. --- litex/soc/cores/esc.py | 2 +- litex/soc/cores/hyperbus.py | 3 ++- litex/soc/cores/led.py | 3 ++- litex/soc/cores/prbs.py | 2 +- litex/soc/cores/uart.py | 3 ++- litex/soc/integration/soc.py | 2 +- litex/soc/interconnect/axi/axi_common.py | 7 +++++-- litex/soc/interconnect/axi/axi_full.py | 5 +++-- litex/soc/interconnect/axi/axi_lite.py | 5 +++-- litex/soc/interconnect/csr_bus.py | 2 +- litex/soc/interconnect/wishbone.py | 2 +- 11 files changed, 22 insertions(+), 14 deletions(-) diff --git a/litex/soc/cores/esc.py b/litex/soc/cores/esc.py index c0e438998..573f47efd 100644 --- a/litex/soc/cores/esc.py +++ b/litex/soc/cores/esc.py @@ -7,9 +7,9 @@ import math from migen import * -from migen.genlib.misc import WaitTimer from litex.gen import LiteXModule +from litex.gen.genlib.misc import WaitTimer from litex.soc.interconnect.csr import * from litex.soc.interconnect import wishbone diff --git a/litex/soc/cores/hyperbus.py b/litex/soc/cores/hyperbus.py index 594c3791e..fbc3d8ddd 100644 --- a/litex/soc/cores/hyperbus.py +++ b/litex/soc/cores/hyperbus.py @@ -7,7 +7,8 @@ # SPDX-License-Identifier: BSD-2-Clause from migen import * -from migen.genlib.misc import WaitTimer + +from litex.gen.genlib.misc import WaitTimer from litex.build.io import DifferentialOutput diff --git a/litex/soc/cores/led.py b/litex/soc/cores/led.py index 2781eb00f..99f8f8168 100644 --- a/litex/soc/cores/led.py +++ b/litex/soc/cores/led.py @@ -8,7 +8,8 @@ import math from migen import * -from migen.genlib.misc import WaitTimer + +from litex.gen.genlib.misc import WaitTimer from litex.soc.interconnect.csr import * from litex.soc.interconnect import wishbone diff --git a/litex/soc/cores/prbs.py b/litex/soc/cores/prbs.py index 662f62fcb..0eb8be971 100644 --- a/litex/soc/cores/prbs.py +++ b/litex/soc/cores/prbs.py @@ -6,10 +6,10 @@ # SPDX-License-Identifier: BSD-2-Clause from migen import * -from migen.genlib.misc import WaitTimer from migen.genlib.cdc import MultiReg from litex.gen import * +from litex.gen.genlib.misc import WaitTimer # Constants ---------------------------------------------------------------------------------------- diff --git a/litex/soc/cores/uart.py b/litex/soc/cores/uart.py index 5a6d147b9..eec88784b 100644 --- a/litex/soc/cores/uart.py +++ b/litex/soc/cores/uart.py @@ -12,7 +12,8 @@ from math import log2 from migen import * from migen.genlib.record import Record from migen.genlib.cdc import MultiReg -from migen.genlib.misc import WaitTimer + +from litex.gen.genlib.misc import WaitTimer from litex.soc.interconnect.csr import * from litex.soc.interconnect.csr_eventmanager import * diff --git a/litex/soc/integration/soc.py b/litex/soc/integration/soc.py index 6f185a5c7..54fbd792d 100644 --- a/litex/soc/integration/soc.py +++ b/litex/soc/integration/soc.py @@ -15,10 +15,10 @@ import datetime from math import log2, ceil from migen import * -from migen.genlib.misc import WaitTimer from litex.gen import colorer from litex.gen import LiteXModule +from litex.gen.genlib.misc import WaitTimer from litex.gen.fhdl.hierarchy import LiteXHierarchyExplorer from litex.compat.soc_core import * diff --git a/litex/soc/interconnect/axi/axi_common.py b/litex/soc/interconnect/axi/axi_common.py index a0744e905..41b666436 100644 --- a/litex/soc/interconnect/axi/axi_common.py +++ b/litex/soc/interconnect/axi/axi_common.py @@ -9,10 +9,13 @@ from migen import * from migen.genlib import roundrobin -from migen.genlib.misc import WaitTimer + +from litex.gen.genlib.misc import WaitTimer + +from litex.build.generic_platform import * from litex.soc.interconnect import stream -from litex.build.generic_platform import * + # AXI Constants ------------------------------------------------------------------------------------ diff --git a/litex/soc/interconnect/axi/axi_full.py b/litex/soc/interconnect/axi/axi_full.py index a6b5e4319..f14d94438 100644 --- a/litex/soc/interconnect/axi/axi_full.py +++ b/litex/soc/interconnect/axi/axi_full.py @@ -9,11 +9,12 @@ from migen import * from migen.genlib import roundrobin -from migen.genlib.misc import WaitTimer -from litex.soc.interconnect import stream +from litex.gen.genlib.misc import WaitTimer + from litex.build.generic_platform import * +from litex.soc.interconnect import stream from litex.soc.interconnect.axi.axi_common import * from litex.soc.interconnect.axi.axi_stream import AXIStreamInterface diff --git a/litex/soc/interconnect/axi/axi_lite.py b/litex/soc/interconnect/axi/axi_lite.py index 388b9b6fc..b336efec5 100644 --- a/litex/soc/interconnect/axi/axi_lite.py +++ b/litex/soc/interconnect/axi/axi_lite.py @@ -9,11 +9,12 @@ from migen import * from migen.genlib import roundrobin -from migen.genlib.misc import WaitTimer -from litex.soc.interconnect import stream +from litex.gen.genlib.misc import WaitTimer + from litex.build.generic_platform import * +from litex.soc.interconnect import stream from litex.soc.interconnect.axi.axi_common import * # AXI-Lite Definition ------------------------------------------------------------------------------ diff --git a/litex/soc/interconnect/csr_bus.py b/litex/soc/interconnect/csr_bus.py index 757bb956e..00a40b7ee 100644 --- a/litex/soc/interconnect/csr_bus.py +++ b/litex/soc/interconnect/csr_bus.py @@ -16,10 +16,10 @@ the configuration and status registers of cores from software. from migen import * from migen.genlib.record import * -from migen.genlib.misc import chooser from migen.util.misc import xdir from litex.gen import * +from litex.gen.genlib.misc import chooser from litex.soc.interconnect import csr from litex.soc.interconnect.csr import CSRStorage diff --git a/litex/soc/interconnect/wishbone.py b/litex/soc/interconnect/wishbone.py index 12143df36..ce8e63314 100644 --- a/litex/soc/interconnect/wishbone.py +++ b/litex/soc/interconnect/wishbone.py @@ -14,9 +14,9 @@ from math import log2 from migen import * from migen.genlib import roundrobin from migen.genlib.record import * -from migen.genlib.misc import split, displacer, chooser, WaitTimer from litex.gen import * +from litex.gen.genlib.misc import split, displacer, chooser, WaitTimer from litex.build.generic_platform import *