diff --git a/migen/fhdl/structure.py b/migen/fhdl/structure.py index 3b4033f83..0ac9b5250 100644 --- a/migen/fhdl/structure.py +++ b/migen/fhdl/structure.py @@ -209,14 +209,14 @@ class Instance: def __init__(self, of, outs=[], ins=[], parameters=[], clkport="", rstport="", name=""): self.of = of if name: - self.name = name + self.name_override = name else: - self.name = of + self.name_override = of def process_io(x): if isinstance(x[1], Signal): return x # override elif isinstance(x[1], BV): - return (x[0], Signal(x[1], self.name + "_" + x[0])) + return (x[0], Signal(x[1], self.name_override + "_" + x[0])) else: raise TypeError self.outs = dict(map(process_io, outs)) diff --git a/migen/fhdl/tools.py b/migen/fhdl/tools.py index 6ba4372dd..60419f8a8 100644 --- a/migen/fhdl/tools.py +++ b/migen/fhdl/tools.py @@ -73,13 +73,16 @@ def group_by_targets(sl): groups.append((targets, [statement])) return groups -def list_inst_outs(i): +def list_inst_ios(i, ins, outs): if isinstance(i, Fragment): - return list_inst_outs(i.instances) + return list_inst_ios(i.instances, ins, outs) else: l = [] for x in i: - l += list(map(lambda x: x[1], list(x.outs.items()))) + if ins: + l += x.ins.values() + if outs: + l += x.outs.values() return set(l) def is_variable(node): diff --git a/migen/fhdl/verilog.py b/migen/fhdl/verilog.py index 7f9ceb94e..5f343cfeb 100644 --- a/migen/fhdl/verilog.py +++ b/migen/fhdl/verilog.py @@ -98,7 +98,7 @@ def _list_comb_wires(f): def _printheader(f, ios, name, ns): sigs = list_signals(f) targets = list_targets(f) - instouts = list_inst_outs(f) + instouts = list_inst_ios(f, False, True) wires = _list_comb_wires(f) r = "module " + name + "(\n" firstp = True @@ -213,7 +213,7 @@ def convert(f, ios=set(), name="top", clk_signal=None, rst_signal=None, return_n if rst_signal is None: rst_signal = Signal(name_override="sys_rst") ios.add(rst_signal) - ns = build_namespace(list_signals(f) | ios) + ns = build_namespace(list_signals(f) | list_inst_ios(f, True, True) | ios) ios |= f.pads