diff --git a/mibuild/platforms/usrp_b100.py b/mibuild/platforms/usrp_b100.py
index add6a5b47..4dfded6fa 100644
--- a/mibuild/platforms/usrp_b100.py
+++ b/mibuild/platforms/usrp_b100.py
@@ -113,9 +113,6 @@ _io = [
 
 
 class Platform(XilinxISEPlatform):
-	xst_opt = """-ifmt MIXED
--opt_mode SPEED
--register_balancing yes"""
 	bitgen_opt = "-g LCK_cycle:6 -g Binary:Yes -g UnusedPin:PullUp"
 	def __init__(self):
 		XilinxISEPlatform.__init__(self, "xc3s1400a-ft256-4", _io,
diff --git a/mibuild/xilinx_ise.py b/mibuild/xilinx_ise.py
index 8018a1fe2..25357ac41 100644
--- a/mibuild/xilinx_ise.py
+++ b/mibuild/xilinx_ise.py
@@ -187,7 +187,6 @@ class XilinxISEPlatform(GenericPlatform):
 	bitstream_ext = ".bit"
 	xst_opt = """-ifmt MIXED
 -opt_mode SPEED
--reduce_control_sets auto
 -register_balancing yes"""
 	map_opt = "-ol high -w"
 	par_opt = "-ol high -w"