From ea2171d32bb784a1c9749ca8683b90e71a3f2427 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Wed, 1 Mar 2023 14:49:08 +0100 Subject: [PATCH] tools/litex_sim: Fix --with-etherbone --with-ethernet case (thanks @g2gps). --- litex/tools/litex_sim.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/litex/tools/litex_sim.py b/litex/tools/litex_sim.py index 85f8f914a..e96bc13d0 100755 --- a/litex/tools/litex_sim.py +++ b/litex/tools/litex_sim.py @@ -272,9 +272,9 @@ class SimSoC(SoCCore): hw_mac = etherbone_mac_address) # SoftCPU - ethmac_region_size = (ethmac.rx_slots.constant + ethmac.tx_slots.constant)*ethmac.slot_size.constant + ethmac_region_size = (self.ethmac.rx_slots.constant + self.ethmac.tx_slots.constant)*self.ethmac.slot_size.constant ethmac_region = SoCRegion(origin=self.mem_map.get("ethmac", None), size=ethmac_region_size, cached=False) - self.bus.add_slave(name="ethmac", slave=ethmac.bus, region=ethmac_region) + self.bus.add_slave(name="ethmac", slave=self.ethmac.bus, region=ethmac_region) if self.irq.enabled: self.irq.add("ethmac", use_loc_if_exists=True) # HW ethernet