From ea8563339f96f2145490a772510545ef20d97af8 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Fri, 28 Feb 2020 22:03:40 +0100 Subject: [PATCH] soc/cores/uart/UARTCrossover: reduce fifo_depth to 1. --- litex/soc/cores/uart.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/litex/soc/cores/uart.py b/litex/soc/cores/uart.py index fc4ec27f2..dd59143f7 100644 --- a/litex/soc/cores/uart.py +++ b/litex/soc/cores/uart.py @@ -272,7 +272,7 @@ class UARTCrossover(UART): def __init__(self, **kwargs): assert kwargs.get("phy", None) == None UART.__init__(self, **kwargs) - self.submodules.xover = UART(tx_fifo_depth=2, rx_fifo_depth=2, rx_fifo_rx_we=True) + self.submodules.xover = UART(tx_fifo_depth=1, rx_fifo_depth=1, rx_fifo_rx_we=True) self.comb += [ self.source.connect(self.xover.sink), self.xover.source.connect(self.sink)