diff --git a/litex/soc/cores/cpu/vexriscv/core.py b/litex/soc/cores/cpu/vexriscv/core.py
index 551bfa837..a7e64b6ed 100644
--- a/litex/soc/cores/cpu/vexriscv/core.py
+++ b/litex/soc/cores/cpu/vexriscv/core.py
@@ -107,6 +107,7 @@ class VexRiscv(CPU, AutoCSR):
     def __init__(self, platform, variant="standard"):
         self.platform         = platform
         self.variant          = variant
+        self.human_name       = CPU_VARIANTS.get(variant, "VexRiscv")
         self.external_variant = None
         self.reset            = Signal()
         self.interrupt        = Signal(32)