diff --git a/litex/boards/platforms/kc705.py b/litex/boards/platforms/kc705.py index 8563938c0..3abde5bb1 100644 --- a/litex/boards/platforms/kc705.py +++ b/litex/boards/platforms/kc705.py @@ -111,18 +111,19 @@ _io = [ IOStandard("LVCMOS25")), ("ddram", 0, - Subsignal("a", Pins( + Subsignal("a", Pins( "AH12 AG13 AG12 AF12 AJ12 AJ13 AJ14 AH14", "AK13 AK14 AF13 AE13 AJ11 AH11 AK10 AK11"), IOStandard("SSTL15")), - Subsignal("ba", Pins("AH9 AG9 AK9"), IOStandard("SSTL15")), - Subsignal("ras_n", Pins("AD9"), IOStandard("SSTL15")), - Subsignal("cas_n", Pins("AC11"), IOStandard("SSTL15")), - Subsignal("we_n", Pins("AE9"), IOStandard("SSTL15")), - Subsignal("cs_n", Pins("AC12"), IOStandard("SSTL15")), - Subsignal("dm", Pins("Y16 AB17 AF17 AE16 AK5 AJ3 AF6 AC7"), + Subsignal("ba", Pins("AH9 AG9 AK9"), IOStandard("SSTL15")), + Subsignal("ras_n", Pins("AD9"), IOStandard("SSTL15")), + Subsignal("cas_n", Pins("AC11"), IOStandard("SSTL15")), + Subsignal("we_n", Pins("AE9"), IOStandard("SSTL15")), + Subsignal("cs_n", Pins("AC12"), IOStandard("SSTL15")), + Subsignal("dm", Pins( + "Y16 AB17 AF17 AE16 AK5 AJ3 AF6 AC7"), IOStandard("SSTL15")), - Subsignal("dq", Pins( + Subsignal("dq", Pins( "AA15 AA16 AC14 AD14 AA17 AB15 AE15 Y15", "AB19 AD16 AC19 AD17 AA18 AB18 AE18 AD18", "AG19 AK19 AG18 AF18 AH19 AJ19 AE19 AD19", @@ -132,32 +133,33 @@ _io = [ "AF1 AF2 AE4 AE3 AF3 AF5 AE1 AE5", "AC1 AD3 AC4 AC5 AE6 AD6 AC2 AD4"), IOStandard("SSTL15_T_DCI")), - Subsignal("dqs_p", Pins("AC16 Y19 AJ18 AH16 AH7 AG2 AG4 AD2"), + Subsignal("dqs_p", Pins("AC16 Y19 AJ18 AH16 AH7 AG2 AG4 AD2"), IOStandard("DIFF_SSTL15")), - Subsignal("dqs_n", Pins("AC15 Y18 AK18 AJ16 AJ7 AH1 AG3 AD1"), + Subsignal("dqs_n", Pins("AC15 Y18 AK18 AJ16 AJ7 AH1 AG3 AD1"), IOStandard("DIFF_SSTL15")), - Subsignal("clk_p", Pins("AG10"), IOStandard("DIFF_SSTL15")), - Subsignal("clk_n", Pins("AH10"), IOStandard("DIFF_SSTL15")), - Subsignal("cke", Pins("AF10"), IOStandard("SSTL15")), - Subsignal("odt", Pins("AD8"), IOStandard("SSTL15")), - Subsignal("reset_n", Pins("AK3"), IOStandard("LVCMOS15")), + Subsignal("clk_p", Pins("AG10"), IOStandard("DIFF_SSTL15")), + Subsignal("clk_n", Pins("AH10"), IOStandard("DIFF_SSTL15")), + Subsignal("cke", Pins("AF10"), IOStandard("SSTL15")), + Subsignal("odt", Pins("AD8"), IOStandard("SSTL15")), + Subsignal("reset_n", Pins("AK3"), IOStandard("LVCMOS15")), Misc("SLEW=FAST"), Misc("VCCAUX_IO=HIGH") ), ("ddram_dual_rank", 0, - Subsignal("a", Pins( + Subsignal("a", Pins( "AH12 AG13 AG12 AF12 AJ12 AJ13 AJ14 AH14", "AK13 AK14 AF13 AE13 AJ11 AH11 AK10 AK11"), IOStandard("SSTL15")), - Subsignal("ba", Pins("AH9 AG9 AK9"), IOStandard("SSTL15")), - Subsignal("ras_n", Pins("AD9"), IOStandard("SSTL15")), - Subsignal("cas_n", Pins("AC11"), IOStandard("SSTL15")), - Subsignal("we_n", Pins("AE9"), IOStandard("SSTL15")), - Subsignal("cs_n", Pins("AC12 AE8"), IOStandard("SSTL15")), - Subsignal("dm", Pins("Y16 AB17 AF17 AE16 AK5 AJ3 AF6 AC7"), + Subsignal("ba", Pins("AH9 AG9 AK9"), IOStandard("SSTL15")), + Subsignal("ras_n", Pins("AD9"), IOStandard("SSTL15")), + Subsignal("cas_n", Pins("AC11"), IOStandard("SSTL15")), + Subsignal("we_n", Pins("AE9"), IOStandard("SSTL15")), + Subsignal("cs_n", Pins("AC12 AE8"), IOStandard("SSTL15")), + Subsignal("dm", Pins( + "Y16 AB17 AF17 AE16 AK5 AJ3 AF6 AC7"), IOStandard("SSTL15")), - Subsignal("dq", Pins( + Subsignal("dq", Pins( "AA15 AA16 AC14 AD14 AA17 AB15 AE15 Y15", "AB19 AD16 AC19 AD17 AA18 AB18 AE18 AD18", "AG19 AK19 AG18 AF18 AH19 AJ19 AE19 AD19", @@ -167,14 +169,14 @@ _io = [ "AF1 AF2 AE4 AE3 AF3 AF5 AE1 AE5", "AC1 AD3 AC4 AC5 AE6 AD6 AC2 AD4"), IOStandard("SSTL15_T_DCI")), - Subsignal("dqs_p", Pins("AC16 Y19 AJ18 AH16 AH7 AG2 AG4 AD2"), + Subsignal("dqs_p", Pins("AC16 Y19 AJ18 AH16 AH7 AG2 AG4 AD2"), IOStandard("DIFF_SSTL15")), - Subsignal("dqs_n", Pins("AC15 Y18 AK18 AJ16 AJ7 AH1 AG3 AD1"), + Subsignal("dqs_n", Pins("AC15 Y18 AK18 AJ16 AJ7 AH1 AG3 AD1"), IOStandard("DIFF_SSTL15")), - Subsignal("clk_p", Pins("AG10 AE11"), IOStandard("DIFF_SSTL15")), - Subsignal("clk_n", Pins("AH10 AF11"), IOStandard("DIFF_SSTL15")), - Subsignal("cke", Pins("AF10 AE10"), IOStandard("SSTL15")), - Subsignal("odt", Pins("AD8 AC10"), IOStandard("SSTL15")), + Subsignal("clk_p", Pins("AG10 AE11"), IOStandard("DIFF_SSTL15")), + Subsignal("clk_n", Pins("AH10 AF11"), IOStandard("DIFF_SSTL15")), + Subsignal("cke", Pins("AF10 AE10"), IOStandard("SSTL15")), + Subsignal("odt", Pins("AD8 AC10"), IOStandard("SSTL15")), Subsignal("reset_n", Pins("AK3"), IOStandard("LVCMOS15")), Misc("SLEW=FAST"), Misc("VCCAUX_IO=HIGH") diff --git a/litex/boards/platforms/kcu105.py b/litex/boards/platforms/kcu105.py index 9ebe1473e..820293b4e 100644 --- a/litex/boards/platforms/kcu105.py +++ b/litex/boards/platforms/kcu105.py @@ -105,40 +105,42 @@ _io = [ "AE17 AH17 AE18 AJ15 AG16 AL17 AK18 AG17", "AF18 AH19 AF15 AD19 AJ14 AG19"), IOStandard("SSTL12_DCI")), - Subsignal("ba", Pins("AF17 AL15"), IOStandard("SSTL12_DCI")), - Subsignal("bg", Pins("AG15"), IOStandard("SSTL12_DCI")), - Subsignal("ras_n", Pins("AF14"), IOStandard("SSTL12_DCI")), # A16 - Subsignal("cas_n", Pins("AG14"), IOStandard("SSTL12_DCI")), # A15 - Subsignal("we_n", Pins("AD16"), IOStandard("SSTL12_DCI")), # A14 - Subsignal("cs_n", Pins("AL19"), IOStandard("SSTL12_DCI")), - Subsignal("act_n", Pins("AH14"), IOStandard("SSTL12_DCI")), - Subsignal("ten", Pins("AH16"), IOStandard("SSTL12_DCI")), - Subsignal("alert_n", Pins("AJ16"), IOStandard("SSTL12_DCI")), - Subsignal("par", Pins("AD18"), IOStandard("SSTL12_DCI")), - Subsignal("dm", Pins("AD21 AE25 AJ21 AM21 AH26 AN26 AJ29 AL32"), + Subsignal("ba", Pins("AF17 AL15"), IOStandard("SSTL12_DCI")), + Subsignal("bg", Pins("AG15"), IOStandard("SSTL12_DCI")), + Subsignal("ras_n", Pins("AF14"), IOStandard("SSTL12_DCI")), # A16 + Subsignal("cas_n", Pins("AG14"), IOStandard("SSTL12_DCI")), # A15 + Subsignal("we_n", Pins("AD16"), IOStandard("SSTL12_DCI")), # A14 + Subsignal("cs_n", Pins("AL19"), IOStandard("SSTL12_DCI")), + Subsignal("act_n", Pins("AH14"), IOStandard("SSTL12_DCI")), + #Subsignal("ten", Pins("AH16"), IOStandard("SSTL12_DCI")), + #Subsignal("alert_n", Pins("AJ16"), IOStandard("SSTL12_DCI")), + #Subsignal("par", Pins("AD18"), IOStandard("SSTL12_DCI")), + Subsignal("dm", Pins("AD21 AE25 AJ21 AM21 AH26 AN26 AJ29 AL32"), IOStandard("POD12_DCI")), - Subsignal("dq", Pins( + Subsignal("dq", Pins( "AE23 AG20 AF22 AF20 AE22 AD20 AG22 AE20", "AJ24 AG24 AJ23 AF23 AH23 AF24 AH22 AG25", - "AL22 AL25 AM20 AK23 AK22 AL24 AL20 AL23", "AM24 AN23 AN24 AP23 AP25 AN22 AP24 AM22", - "AH28 AK26 AK28 AM27 AJ28 AH27 AK27 AM26", "AL30 AP29 AM30 AN28 AL29 AP28 AM29 AN27", - "AH31 AH32 AJ34 AK31 AJ31 AJ30 AH34 AK32", - "AN33 AP33 AM34 AP31 AM32 AN31 AL34 AN32", - ), - IOStandard("POD12_DCI")), - Subsignal("dqs_p", Pins("AG21 AH24 AJ20 AP20 AL27 AN29 AH33 AN34"), - IOStandard("DIFF_POD12")), - Subsignal("dqs_n", Pins("AH21 AJ25 AK20 AP21 AL28 AP30 AJ33 AP34"), - IOStandard("DIFF_POD12")), - Subsignal("clk_p", Pins("AE16"), IOStandard("DIFF_SSTL12_DCI")), - Subsignal("clk_n", Pins("AE15"), IOStandard("DIFF_SSTL12_DCI")), - Subsignal("cke", Pins("AD15"), IOStandard("SSTL12_DCI")), - Subsignal("odt", Pins("AJ18"), IOStandard("SSTL12_DCI")), + "AN33 AP33 AM34 AP31 AM32 AN31 AL34 AN32"), + IOStandard("POD12_DCI"), + Misc("PRE_EMPHASIS=RDRV_240"), + Misc("EQUALIZATION=EQ_LEVEL2")), + Subsignal("dqs_p", Pins("AG21 AH24 AJ20 AP20 AL27 AN29 AH33 AN34"), + IOStandard("DIFF_POD12_DCI"), + Misc("PRE_EMPHASIS=RDRV_240"), + Misc("EQUALIZATION=EQ_LEVEL2")), + Subsignal("dqs_n", Pins("AH21 AJ25 AK20 AP21 AL28 AP30 AJ33 AP34"), + IOStandard("DIFF_POD12_DCI"), + Misc("PRE_EMPHASIS=RDRV_240"), + Misc("EQUALIZATION=EQ_LEVEL2")), + Subsignal("clk_p", Pins("AE16"), IOStandard("DIFF_SSTL12_DCI")), + Subsignal("clk_n", Pins("AE15"), IOStandard("DIFF_SSTL12_DCI")), + Subsignal("cke", Pins("AD15"), IOStandard("SSTL12_DCI")), + Subsignal("odt", Pins("AJ18"), IOStandard("SSTL12_DCI")), Subsignal("reset_n", Pins("AL18"), IOStandard("LVCMOS12")), Misc("SLEW=FAST"), ), diff --git a/litex/boards/targets/kcu105.py b/litex/boards/targets/kcu105.py index 36601746a..645962616 100755 --- a/litex/boards/targets/kcu105.py +++ b/litex/boards/targets/kcu105.py @@ -124,7 +124,7 @@ class EthernetSoC(BaseSoC): interface = "wishbone", endianness = self.cpu.endianness) self.add_memory_region("ethmac", self.mem_map["ethmac"], 0x2000, type="io") - self.add_wb_slave(self.mem_regions["ethmac"].origin, self.ethmac.bus, 0x2000) + self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus, 0x2000) self.add_csr("ethmac") self.add_interrupt("ethmac") # timing constraints diff --git a/litex/boards/targets/nexys_video.py b/litex/boards/targets/nexys_video.py index 19df6338b..9773f9ac3 100755 --- a/litex/boards/targets/nexys_video.py +++ b/litex/boards/targets/nexys_video.py @@ -89,8 +89,8 @@ class EthernetSoC(BaseSoC): dw = 32, interface = "wishbone", endianness = self.cpu.endianness) - self.add_memory_region("ethmac", self.mem_map["ethmac"], 0x2000, type="io") self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus, 0x2000) + self.add_memory_region("ethmac", self.mem_map["ethmac"], 0x2000, type="io") self.add_csr("ethmac") self.add_interrupt("ethmac") # timing constraints diff --git a/litex/boards/targets/ulx3s.py b/litex/boards/targets/ulx3s.py index 0869069bb..5ba068faa 100755 --- a/litex/boards/targets/ulx3s.py +++ b/litex/boards/targets/ulx3s.py @@ -5,17 +5,18 @@ # License: BSD import argparse +import sys from migen import * from migen.genlib.resetsync import AsyncResetSynchronizer -from litex.boards.platforms import ulx3s +from litex_boards.platforms import ulx3s from litex.soc.cores.clock import * from litex.soc.integration.soc_sdram import * from litex.soc.integration.builder import * -from litedram.modules import MT48LC16M16 +from litedram import modules as litedram_modules from litedram.phy import GENSDRPHY # CRG ---------------------------------------------------------------------------------------------- @@ -27,33 +28,32 @@ class _CRG(Module): # # # - # clk / rst + # Clk / Rst clk25 = platform.request("clk25") rst = platform.request("rst") - platform.add_period_constraint(clk25, 40.0) + platform.add_period_constraint(clk25, 1e9/25e6) - # pll + # PLL self.submodules.pll = pll = ECP5PLL() self.comb += pll.reset.eq(rst) pll.register_clkin(clk25, 25e6) - pll.create_clkout(self.cd_sys, sys_clk_freq, phase=11) + pll.create_clkout(self.cd_sys, sys_clk_freq, phase=11) pll.create_clkout(self.cd_sys_ps, sys_clk_freq, phase=20) - self.specials += AsyncResetSynchronizer(self.cd_sys, rst) + self.specials += AsyncResetSynchronizer(self.cd_sys, ~pll.locked | rst) - # sdram clock + # SDRAM clock self.comb += platform.request("sdram_clock").eq(self.cd_sys_ps.clk) - # Stop ESP32 from resetting FPGA - wifi_gpio0 = platform.request("wifi_gpio0") - self.comb += wifi_gpio0.eq(1) + # Prevent ESP32 from resetting FPGA + self.comb += platform.request("wifi_gpio0").eq(1) # BaseSoC ------------------------------------------------------------------------------------------ class BaseSoC(SoCSDRAM): - def __init__(self, device="LFE5U-45F", toolchain="diamond", **kwargs): - platform = ulx3s.Platform(device=device, toolchain=toolchain) - sys_clk_freq = int(50e6) + def __init__(self, device="LFE5U-45F", toolchain="diamond", + sys_clk_freq=int(50e6), sdram_module_cls="MT48LC16M16", **kwargs): + platform = ulx3s.Platform(device=device, toolchain=toolchain) # SoCSDRAM --------------------------------------------------------------------------------- SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs) @@ -63,10 +63,10 @@ class BaseSoC(SoCSDRAM): # SDR SDRAM -------------------------------------------------------------------------------- if not self.integrated_main_ram_size: self.submodules.sdrphy = GENSDRPHY(platform.request("sdram"), cl=2) - sdram_module = MT48LC16M16(sys_clk_freq, "1:1") + sdram_module = getattr(litedram_modules, sdram_module_cls)(sys_clk_freq, "1:1") self.register_sdram(self.sdrphy, - geom_settings = sdram_module.geom_settings, - timing_settings = sdram_module.timing_settings) + sdram_module.geom_settings, + sdram_module.timing_settings) # Build -------------------------------------------------------------------------------------------- @@ -76,11 +76,18 @@ def main(): help='gateware toolchain to use, diamond (default) or trellis') parser.add_argument("--device", dest="device", default="LFE5U-45F", help='FPGA device, ULX3S can be populated with LFE5U-45F (default) or LFE5U-85F') + parser.add_argument("--sys-clk-freq", default=50e6, + help="system clock frequency (default=50MHz)") + parser.add_argument("--sdram-module", default="MT48LC16M16", + help="SDRAM module: MT48LC16M16, AS4C32M16 or AS4C16M16 (default=MT48LC16M16)") builder_args(parser) soc_sdram_args(parser) args = parser.parse_args() - soc = BaseSoC(device=args.device, toolchain=args.toolchain, **soc_sdram_argdict(args)) + soc = BaseSoC(device=args.device, toolchain=args.toolchain, + sys_clk_freq=int(float(args.sys_clk_freq)), + sdram_module_cls=args.sdram_module, + **soc_sdram_argdict(args)) builder = Builder(soc, **builder_argdict(args)) builder.build() diff --git a/litex/boards/targets/versa_ecp5.py b/litex/boards/targets/versa_ecp5.py index 2ee57a207..e26475930 100755 --- a/litex/boards/targets/versa_ecp5.py +++ b/litex/boards/targets/versa_ecp5.py @@ -66,7 +66,7 @@ class _CRG(Module): i_RST = self.cd_sys2x.rst, o_CDIVX = self.cd_sys.clk), AsyncResetSynchronizer(self.cd_init, ~por_done | ~pll.locked | ~rst_n), - AsyncResetSynchronizer(self.cd_sys, ~por_done | ~pll.locked | ~rst_n) + AsyncResetSynchronizer(self.cd_sys, ~por_done | ~pll.locked | ~rst_n) ] # BaseSoC ------------------------------------------------------------------------------------------