diff --git a/litex/soc/cores/clock.py b/litex/soc/cores/clock.py
index 252cd4916..a36f9a2f8 100644
--- a/litex/soc/cores/clock.py
+++ b/litex/soc/cores/clock.py
@@ -102,17 +102,22 @@ class XilinxClocking(Module, AutoCSR):
 
         # # #
 
+        den_pipe = Signal()
+        dwe_pipe = Signal()
+
         drp_drdy = Signal()
         self.params.update(
             i_DCLK  = ClockSignal(),
-            i_DWE   = self.drp_write.re,
-            i_DEN   = self.drp_read.re | self.drp_write.re,
+            i_DWE   = dwe_pipe,
+            i_DEN   = den_pipe,
             o_DRDY  = drp_drdy,
             i_DADDR = self.drp_adr.storage,
             i_DI    = self.drp_dat_w.storage,
             o_DO    = self.drp_dat_r.status
         )
         self.sync += [
+            den_pipe.eq(self.drp_read.re | self.drp_write.re),
+            dwe_pipe.eq(self.drp_write.re),
             If(self.drp_read.re | self.drp_write.re,
                 self.drp_drdy.status.eq(0)
             ).Elif(drp_drdy,
diff --git a/litex/soc/cores/xadc.py b/litex/soc/cores/xadc.py
index 178313b78..b6337fbe5 100644
--- a/litex/soc/cores/xadc.py
+++ b/litex/soc/cores/xadc.py
@@ -43,6 +43,7 @@ class XADC(Module, AutoCSR):
         self.dadr = Signal(7)
         self.di   = Signal(16)
         self.do   = Signal(16)
+        self.drp_en = Signal()
         self.specials += Instance("XADC",
             # From ug480
             p_INIT_40=0x9000, p_INIT_41=0x2ef0, p_INIT_42=0x0400,
@@ -77,8 +78,10 @@ class XADC(Module, AutoCSR):
             o_DO        = self.do
         )
         self.comb += [
-            self.den.eq(eoc),
-            self.dadr.eq(channel),
+            If(~self.drp_en,
+                self.den.eq(eoc),
+                self.dadr.eq(channel),
+            )
         ]
 
         # Channels update --------------------------------------------------------------------------
@@ -113,16 +116,20 @@ class XADC(Module, AutoCSR):
 
         # # #
 
+        den_pipe = Signal() # add a register to ease timing closure of den
+
         self.comb += [
-            self.dwe.eq(self.drp_write.re),
             self.di.eq(self.drp_dat_w.storage),
             self.drp_dat_r.status.eq(self.do),
-            If(self.drp_enable.storage,
-                self.den.eq(self.drp_read.re | self.drp_write.re),
-                self.dadr.eq(self.drp_adr.storage),
-            ),
+            If(self.drp_en,
+               self.den.eq(den_pipe),
+               self.dadr.eq(self.drp_adr.storage),
+            )
         ]
         self.sync += [
+            self.dwe.eq(self.drp_write.re),
+            self.drp_en.eq(self.drp_enable.storage),
+            den_pipe.eq(self.drp_read.re | self.drp_write.re),
             If(self.drp_read.re | self.drp_write.re,
                 self.drp_drdy.status.eq(0)
             ).Elif(self.drdy,